Seung-Myeong Yu

According to our database, Seung-Myeong Yu authored at least 7 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 0.74 pJ/bit 10 Gbps PAM-4 Transceiver with Triple TIA Termination and Power-saving Addition-only Driving for Parallel Memory Interface Channels.

Junsen He, Kiho Seong, Dong-Hyun Yoon, Seung-Myeong Yu, Junyoung Song, Youngdon Choi, Jung-Hwan Choi, Tony Tae-Hyoung Kim

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025

A 1.58 pJ/b 9 G bps Reference-Less Clock and Data Recovery Circuit With Sigma Range Detector.

Jongchan An, Seung-Myeong Yu, Gwangmyeong An, Songi Cheon, Hyunsu Jang, Junyoung Song

IEEE Trans. Circuits Syst. II Express Briefs, July, 2025

2024

A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit.

Jongchan An, Seung-Myeong Yu, Gwangmyeong An, Bongsu Kim, Hyunsu Jang, Sewook Hwang, Junyoung Song

IEEE Trans. Very Large Scale Integr. Syst., June, 2024

An 11 Gb/s 0.376 pJ/Bit Capacitor-Less Dicode Transceiver With Pattern-Dependent Equalizations TIA Termination for Parallel DRAM Interfaces.

Hyunsu Park, Seung-Myeong Yu, Junyoung Song

IEEE Access, 2024

2021

Digital LDO with reference-less adaptive CLK generation and bit-shifting Coarse-Fine-control.

Wooyoung Choi, Seung-Myeong Yu, Yunha Kang, Junyoung Song

Proceedings of the 18th International SoC Design Conference, 2021

A 20Gb/s/pin Single-ended Transmitter with FEXT Compensation Technique.

Seung-Myeong Yu, Yunha Kang, Wooyoung Choi, Jongchan An, Junyoung Song

Proceedings of the International Conference on Electronics, Information, and Communication, 2021

A 28Gb/s quad-rate 1-FIR 2-IIR DFE with 20dB Loss Compensation in 65nm CMOS Process.

Yunha Kang, Seung-Myeong Yu, Jongchan An, Wooyoung Choi, Junyoung Song

Proceedings of the International Conference on Electronics, Information, and Communication, 2021