Youngdon Choi
This page is a disambiguation page, it actually contains multiple papers from persons of the same or a similar name.
Bibliography
2026
A Time-Based PAM-4 Transceiver Using Linear Voltage-to-Time Converter and Single Path PAM-4 Decoder with Fast-Stochastic Calibration.
Circuits Syst. Signal Process., February, 2026
A 28-Gb/mm<sup>2</sup> 4XX-Layer 1-Tb 3-b/Cell WF-Bonding 3D-nand Flash With 5.6-Gb/s/Pin IOs.
IEEE J. Solid State Circuits, January, 2026
A 0.74 pJ/bit 10 Gbps PAM-4 Transceiver with Triple TIA Termination and Power-saving Addition-only Driving for Parallel Memory Interface Channels.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
2025
A Hybrid Approach to Physical and Deep Learning Models for Radar-Based Precipitation Nowcasting.
IEEE Trans. Geosci. Remote. Sens., 2025
Toward reproducible and interoperable environmental modeling: Integration of HydroShare with server-side methods for exposing large-extent spatial datasets to models.
Environ. Model. Softw., 2025
30.1 A 28Gb/mm<sup>2</sup>4XX-Layer 1Tb 3b/Cell WF-Bonding 3D-NAND Flash with 5.6Gb/s/Pin IOs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2024
A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024
A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3.
IEEE J. Solid State Circuits, October, 2024
An extensible schema for capturing environmental model metadata: Implementation in the HydroShare online data repository.
Environ. Model. Softw., 2024
A 10.5 Gbps 0.55 pJ/bit PAM-3 Transceiver Using a Self-driven Dual TIA Receiver and Floating Impedance Matching for Parallel On-chip Transmission Lines.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2023
Comparing containerization-based approaches for reproducible computational modeling of environmental systems.
Environ. Model. Softw., September, 2023
A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
Building cyberinfrastructure for the reuse and reproducibility of complex hydrologic modeling studies.
Environ. Model. Softw., 2023
A Time-Based PAM-4 Transceiver Using Single Path Decoder and Fast-Stochastic Calibration Techniques.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the 19th International SoC Design Conference, 2022
A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
Toward open and reproducible environmental modeling by integrating online data repositories, computational environments, and model Application Programming Interfaces.
Environ. Model. Softw., 2021
A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics.
Proceedings of the 47th ESSCIRC 2021, 2021
A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
Environ. Model. Softw., 2020
13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Proceedings of the Practice and Experience in Advanced Research Computing on Rise of the Machines (learning), 2019
Proceedings of the Parallel Computing: Technology Trends, 2019
A 512Gb 3-bit/Cell 3D 6<sup>th</sup>-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
IEEE J. Solid State Circuits, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
Thermal Characteristics of a Primary Surface Heat Exchanger with Corrugated Channels.
Entropy, 2016
2015
Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Heat Transfer and Pressure Drop Characteristics in Straight Microchannel of Printed Circuit Heat Exchangers.
Entropy, 2015
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2009
BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel.
IEEE J. Solid State Circuits, 2009
2003
Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery.
IEEE Trans. Circuits Syst. II Express Briefs, 2003
2002
A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit.
IEEE J. Solid State Circuits, 2002