Sewook Hwang

According to our database1, Sewook Hwang authored at least 22 papers between 2011 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces.
IEEE J. Solid State Circuits, 2019

2018
A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels.
IEEE Trans. Very Large Scale Integr. Syst., 2016

An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

2013
A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 0.008 mm<sup>2</sup> 500 µW 469 kS/s Frequency-to-Digital Converter Based CMOS Temperature Sensor With Process Variation Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile.
IEEE J. Solid State Circuits, 2012

A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13µm CMOS.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A 0.076mm<sup>2</sup> 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011


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