Shahana Thottathikkulam Kassim

According to our database1, Shahana Thottathikkulam Kassim authored at least 13 papers between 2006 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
New Biclique Cryptanalysis on Full-Round PRESENT-80 Block Cipher.
SN Comput. Sci., 2020

Efficient modular hybrid adders and Radix-4 booth multipliers for DSP applications.
Microelectron. J., 2020

2019
High throughput FIR filter architectures using retiming and modified CSLA based adders.
IET Circuits Devices Syst., 2019

Isolated Switched Boost DC-DC Converter with Coupled Inductor and Transformer.
Proceedings of the TENCON 2019, 2019

2017
Multi-Stage Noise Shaping ΔΣ Modulator with Enhanced Noise Shaping for Low Power Wideband Applications.
J. Low Power Electron., 2017

2016
A multi-mode MASH ΣΑ modulator for low power wideband applications.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

2008
RNS Based Programmable Multi-Mode Decimation Filter for WCDMA and WiMAX.
Proceedings of the 67th IEEE Vehicular Technology Conference, 2008

Fixed Point Decimal Multiplication Using RPS Algorithm.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

Dual-mode RNS based programmable decimation filter for WCDMA and WLANa.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

RRNS-Convolutional encoded concatenated code for OFDM based wireless communication.
Proceedings of the 16th International Conference on Networks, 2008

2007
A New Look at Reversible Logic Implementation of Decimal Adder.
Proceedings of the International Symposium on System-on-Chip, 2007

Genetic Algorithm-Based Combinational Logic Synthesis Using Universal Logic Modules.
Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007

2006
Delay-Reduced Combinational Logic Synthesis using Multiplexers.
Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006


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