Jimson Mathew
According to our database^{1},
Jimson Mathew
authored at least 170 papers
between 1999 and 2021.
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Bibliography
2021
Pattern Recognit. Lett., 2021
Expert Syst. Appl., 2021
2020
A particle swarm optimizationbased feature selection for unsupervised transfer learning.
Soft Comput., 2020
Semisupervised orthogonal discriminant analysis with relative distance : integration with a MOO approach.
Soft Comput., 2020
Intelligent Residential Energy Management System Using Deep Reinforcement Learning.
IEEE Syst. J., 2020
Abnormal activity detection using shear transformed spatiotemporal regions at the surveillance network edge.
Multim. Tools Appl., 2020
Interactive Robotic Testbed for Performance Assessment of Machine Learning based Computer Vision Techniques.
J. Inf. Sci. Eng., 2020
Image Vis. Comput., 2020
Improved subspace clustering algorithm using multiobjective framework and subspace optimization.
Expert Syst. Appl., 2020
CoRR, 2020
CoRR, 2020
CoRR, 2020
Particle swarm optimization based parameter selection technique for unsupervised discriminant analysis in transfer learning framework.
Appl. Intell., 2020
Enabling Hardware Performance Counters for MicrokernelBased Virtualization on Embedded Systems.
IEEE Access, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
A Particle Swarm Optimization Based Joint Geometrical and Statistical Alignment Approach with Laplacian Regularization.
Proceedings of the Neural Information Processing  27th International Conference, 2020
Proceedings of the Neural Information Processing  27th International Conference, 2020
A Modified Joint Geometrical and Statistical Alignment Approach for LowResolution Face Recognition.
Proceedings of the Neural Information Processing  27th International Conference, 2020
Proceedings of the Neural Information Processing  27th International Conference, 2020
Proceedings of the IEEE International Conference on Image Processing, 2020
Routing of Delivery Trucks in a Battery Swapping System with Partial Delivery Option.
Proceedings of the eEnergy '20: The Eleventh ACM International Conference on Future Energy Systems, 2020
2019
HighPerformance CNN Accelerator on FPGA Using Unified WinogradGEMM Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Correlation power analysis and effective defense approach on light encryption device block cipher.
Secur. Priv., 2019
Fusion of evolvable genome structure and multiobjective optimization for subspace clustering.
Pattern Recognit., 2019
Knowl. Based Syst., 2019
J. Low Power Electron., 2019
J. Circuits Syst. Comput., 2019
A novel unsupervised GlobalityLocality Preserving Projections in transfer learning.
Image Vis. Comput., 2019
Realtime singleview face detection and face recognition based on aggregate channel feature.
Int. J. Biom., 2019
Autoencoderbased abnormal activity detection using parallelepiped spatiotemporal region.
IET Comput. Vis., 2019
Radix4<sup>3</sup> based twodimensional FFT architecture with efficient data reordering scheme.
IET Comput. Digit. Tech., 2019
A kernel semisupervised distance metric learning with relative distance: Integration with a MOO approach.
Expert Syst. Appl., 2019
IEEE Access, 2019
IEEE Access, 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Proceedings of the TENCON 2019, 2019
Proceedings of the 32nd IEEE International SystemonChip Conference, 2019
The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors.
Proceedings of the 25th IEEE International Symposium on OnLine Testing and Robust System Design, 2019
Proceedings of the Neural Information Processing  26th International Conference, 2019
Unified Framework for Visual Domain Adaptation Using GlobalityLocality Preserving Projections.
Proceedings of the Neural Information Processing  26th International Conference, 2019
Proceedings of the Neural Information Processing  26th International Conference, 2019
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Multiobjective Approach for SemiSupervised Discriminant Analysis with Relative Distance.
Proceedings of the IEEE Congress on Evolutionary Computation, 2019
Online feature selection for multilabel classification in multiobjective optimization framework.
Proceedings of the ASONAM '19: International Conference on Advances in Social Networks Analysis and Mining, 2019
2018
A Differential QuantizerBased Error Feedback Modulator for AnalogtoDigital Converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A Differentially Quantized Bandpass Error Feedback Modulator for ADCs in Digital Radio.
Circuits Syst. Signal Process., 2018
A Hardware Accelerator for Convolutional Neural Network Using Fast Fourier Transform.
Proceedings of the VLSI Design and Test  22nd International Symposium, 2018
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018
Proceedings of the Neural Information Processing  25th International Conference, 2018
Proceedings of the Neural Information Processing  25th International Conference, 2018
A Multikernel Semisupervised Metric Learning Using Multiobjective Optimization Approach.
Proceedings of the Neural Information Processing  25th International Conference, 2018
Multiobjective optimization based subspace clustering using evolvable genome structure.
Proceedings of the Genetic and Evolutionary Computation Conference Companion, 2018
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
Two dimensional FFT architecture based on radix4<sup>3</sup> algorithm with efficient output reordering.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
45nm BitInterleaving Differential 10T Low Leakage FinFET Based SRAM with ColumnWise Write Access Control.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018
2017
Improved Multiple FaultsAware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits.
IEEE Trans. Reliab., 2017
A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis.
IEEE Trans. Emerg. Top. Comput., 2017
ACM Trans. Embed. Comput. Syst., 2017
Binary Decision Diagram Assisted Modeling of FPGABased Physically Unclonable Function by Genetic Programming.
IEEE Trans. Computers, 2017
J. Low Power Electron., 2017
J. Low Power Electron., 2017
J. Low Power Electron., 2017
An antenna selection scheme with MRE and AWC for decision fusion in cognitive radio.
Trans. Emerg. Telecommun. Technol., 2017
Proceedings of the 23rd IEEE International Symposium on OnLine Testing and Robust System Design, 2017
2016
Circuits Syst. Signal Process., 2016
A Novel Excess SturdyMASHLoopDelay Compensated CrossCoupled SigmaDelta Modulator.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 22nd IEEE International Symposium on OnLine Testing and Robust System Design, 2016
2015
A LowComplexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2<sup>m</sup>).
IEEE Trans. Very Large Scale Integr. Syst., 2015
A LowCost Unified Design Methodology for Secure Test and Intellectual Property Core Protection.
IEEE Trans. Reliab., 2015
ACM Trans. Embed. Comput. Syst., 2015
J. Low Power Electron., 2015
A Multiple Input Variable Output Switched Capacitor DCDC Converter for Harnessing Renewable Energy and Powering LEDs.
J. Low Power Electron., 2015
Integr., 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
Exploring errortolerant lowpower multipleoutput read scheme for memristorbased memory arrays.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
2014
Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems.
J. Low Power Electron., 2014
A Novel Integrated Circuit Design Methodology Using Dynamic Library Concept with Reduced NonRecurring Engineering Cost and TimetoMarket.
J. Low Power Electron., 2014
J. Low Power Electron., 2014
J. Low Power Electron., 2014
TQCRmedia access control: twolevel quality of service provisioning media access control protocol for cognitive radio network.
IET Networks, 2014
VerilogA Based Effective Complementary Resistive Switch Model for Simulations and Analysis.
IEEE Embed. Syst. Lett., 2014
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
Dual Extended Noise Shaping for High Performance CrossCoupled SigmaDelta Modulators.
Proceedings of the Eighth International Conference on Next Generation Mobile Apps, 2014
Proceedings of the Eighth International Conference on Next Generation Mobile Apps, 2014
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Complementary resistive switch based stateful logic operations using material implication.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Energy Aware Spectrum Decision Framework for Cognitive Radio Network: A Spectrum Decision Framework for Cognitive Radio Network with Energy Awareness.
J. Low Power Electron., 2013
J. Low Power Electron., 2013
Cellular Automata Approach for a Low Power Fusion Center to Evaluate Spectrum Status and Coverage Area in Cognitive Radios.
J. Low Power Electron., 2013
Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity.
Comput. Electr. Eng., 2013
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
A Novel Physical Synthesis Methodology in the VLSI Design Automation by Introducing Dynamic Library Concept.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
A Novel and Unified Digital IC Design and Automation Methodology with Reduced NRE Cost and TimetoMarket.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of NanoCMOS Circuits.
J. Low Power Electron., 2012
VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases.
Proceedings of the Progress in VLSI Design and Test  16th International Symposium, 2012
RAEF: A Power Normalized SystemLevel Reliability Analysis and Estimation Framework.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
2011
J. Signal Process. Syst., 2011
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
A VariationAware Taylor Expansion DiagramBased Approach for NanoCMOS RegisterTransfer Level Leakage Optimization.
J. Low Power Electron., 2011
Faulttolerant deBruijn graph based multipurpose architecture and routing protocol for wireless sensor networks.
Int. J. Sens. Networks, 2011
PseudoParallel Datapath Structure for Power Optimal Implementation of 128pt FFT/IFFT for WPAN.
Circuits Syst. Signal Process., 2011
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Statistical Blockade Method for Fast Robustness Estimation and Compensation of NanoCMOS Arithmetic Circuits.
Proceedings of the International Symposium on Electronic System Design, 2011
Proceedings of the International Symposium on Electronic System Design, 2011
Proceedings of the International Symposium on Electronic System Design, 2011
A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of GF(2<sup>m</sup>).
IEEE Trans. Very Large Scale Integr. Syst., 2010
Test Generation in Systolic Architecture for Multiplication Over GF(2 <sup>m</sup>).
IEEE Trans. Very Large Scale Integr. Syst., 2010
Simplified bit parallel systolic multipliers for special class of galois field (2<sup>m</sup>) with testability.
IET Comput. Digit. Tech., 2010
IET Comput. Digit. Tech., 2010
Comput. J., 2010
Proceedings of the 18th IEEE/IFIP VLSISoC 2010, 2010
Fault diagnosis in multi layered De Bruijn based architectures for sensor networks.
Proceedings of the Eigth Annual IEEE International Conference on Pervasive Computing and Communications, 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
2009
An O(m<sup>2</sup>)depth quantum algorithm for the elliptic curve discrete logarithm problem over GF(2<sup>m</sup>)<sup>a</sup>.
Quantum Inf. Comput., 2009
IET Comput. Digit. Tech., 2009
Single Ended Static Random Access Memory for LowVdd, HighSpeed Embedded Systems.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the 15th IEEE International OnLine Testing Symposium (IOLTS 2009), 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
ACM Trans. Design Autom. Electr. Syst., 2008
GfXpress: A Technique for Synthesis and Optimization of GF(2<sup>m</sup>) Polynomials.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Trans. Computers, 2008
Realization of Low Power HighSpeed Channel Filters with Stringent Adjacent Channel Attenuation Specifications for Wireless Communication Receivers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Eng. Lett., 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
On the Design and Optimization of a Quantum PolynomialTime Attack on Elliptic Curve Cryptography.
Proceedings of the Theory of Quantum Computation, 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the IEEE International Conference on Systems, 2008
Proceedings of the IEEE International Conference on Systems, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 14th IEEE International OnLine Testing Symposium (IOLTS 2008), 2008
Design Techniques for BitParallel Galois Field Multipliers with OnLine Single Error Correction and Double Error Detection.
Proceedings of the 14th IEEE International OnLine Testing Symposium (IOLTS 2008), 2008
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs.
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
A triplemode feedforward sigmadelta modulator design for GSM / WCDMA / WLAN applications.
Proceedings of the 2007 IEEE International SOC Conference, 2007
SEUMitigation Placement and Routing Algorithms and Their Impact in SRAMBased FPGAs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 13th IEEE International OnLine Testing Symposium (IOLTS 2007), 2007
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007
Proceedings of the 10th International Conference on Information Technology, 2007
Proceedings of the 10th International Conference on Information Technology, 2007
2006
An efficient technique for synthesis and optimization of polynomials in GF(2<sup><i>m</i></sup>).
Proceedings of the 2006 International Conference on ComputerAided Design, 2006
Proceedings of the Eleventh Annual IEEE International HighLevel Design Validation and Test Workshop 2006, 2006
2002
Proceedings of the 17th IEEE International Symposium on Defect and FaultTolerance in VLSI Systems (DFT 2002), 2002
2000
Proceedings of the 10th European Signal Processing Conference, 2000
1999
Residuetobinary arithmetic converter for moduli set {2n 1, 2n, 2n+1, 2n+1 1}.
Proceedings of the IEEEEURASIP Workshop on Nonlinear Signal and Image Processing (NSIP'99), 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999