Jimson Mathew

According to our database1, Jimson Mathew authored at least 170 papers between 1999 and 2021.

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Bibliography

2021
Evolutionary multi-objective optimization based overlapping subspace clustering.
Pattern Recognit. Lett., 2021

Kernelized Unified Domain Adaptation on Geometrical Manifolds.
Expert Syst. Appl., 2021

2020
A particle swarm optimization-based feature selection for unsupervised transfer learning.
Soft Comput., 2020

Semi-supervised orthogonal discriminant analysis with relative distance : integration with a MOO approach.
Soft Comput., 2020

Intelligent Residential Energy Management System Using Deep Reinforcement Learning.
IEEE Syst. J., 2020

Abnormal activity detection using shear transformed spatio-temporal regions at the surveillance network edge.
Multim. Tools Appl., 2020

Interactive Robotic Testbed for Performance Assessment of Machine Learning based Computer Vision Techniques.
J. Inf. Sci. Eng., 2020

Monocular depth estimation with SPN loss.
Image Vis. Comput., 2020

Improved subspace clustering algorithm using multi-objective framework and subspace optimization.
Expert Syst. Appl., 2020

Multi-Modal Detection of Alzheimer's Disease from Speech and Text.
CoRR, 2020

A Deep Learning Framework for COVID Outbreak Prediction.
CoRR, 2020

Monocular Depth Estimators: Vulnerabilities and Attacks.
CoRR, 2020

Particle swarm optimization based parameter selection technique for unsupervised discriminant analysis in transfer learning framework.
Appl. Intell., 2020

Enabling Hardware Performance Counters for Microkernel-Based Virtualization on Embedded Systems.
IEEE Access, 2020

Statistical and Geometrical Alignment using Metric Learning in Domain Adaptation.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

A Particle Swarm Optimization Based Joint Geometrical and Statistical Alignment Approach with Laplacian Regularization.
Proceedings of the Neural Information Processing - 27th International Conference, 2020

A Feature Selection Approach to Visual Domain Adaptation in Classification.
Proceedings of the Neural Information Processing - 27th International Conference, 2020

A Modified Joint Geometrical and Statistical Alignment Approach for Low-Resolution Face Recognition.
Proceedings of the Neural Information Processing - 27th International Conference, 2020

Online Multi-objective Subspace Clustering for Streaming Data.
Proceedings of the Neural Information Processing - 27th International Conference, 2020

Self-Attention Dense Depth Estimation Network for Unrectified Video Sequences.
Proceedings of the IEEE International Conference on Image Processing, 2020

Routing of Delivery Trucks in a Battery Swapping System with Partial Delivery Option.
Proceedings of the e-Energy '20: The Eleventh ACM International Conference on Future Energy Systems, 2020

2019
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Correlation power analysis and effective defense approach on light encryption device block cipher.
Secur. Priv., 2019

Fusion of evolvable genome structure and multi-objective optimization for subspace clustering.
Pattern Recognit., 2019

A framework for semi-supervised metric transfer learning on manifolds.
Knowl. Based Syst., 2019

Selected Articles from the ISED 2018 Conference.
J. Low Power Electron., 2019

Memristor Based Planar Tunable RF Circuits.
J. Circuits Syst. Comput., 2019

A novel unsupervised Globality-Locality Preserving Projections in transfer learning.
Image Vis. Comput., 2019

Real-time single-view face detection and face recognition based on aggregate channel feature.
Int. J. Biom., 2019

Autoencoder-based abnormal activity detection using parallelepiped spatio-temporal region.
IET Comput. Vis., 2019

Radix-4<sup>3</sup> based two-dimensional FFT architecture with efficient data reordering scheme.
IET Comput. Digit. Tech., 2019

A kernel semi-supervised distance metric learning with relative distance: Integration with a MOO approach.
Expert Syst. Appl., 2019

A New Transfer Learning Algorithm in Semi-Supervised Setting.
IEEE Access, 2019

A Kernelized Unified Framework for Domain Adaptation.
IEEE Access, 2019

UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Isolated Switched Boost DC-DC Converter with Coupled Inductor and Transformer.
Proceedings of the TENCON 2019, 2019

Efficient Hardware Acceleration of Convolutional Neural Networks.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Semi-supervised Regularized Coplanar Discriminant Analysis.
Proceedings of the Neural Information Processing - 26th International Conference, 2019

Unified Framework for Visual Domain Adaptation Using Globality-Locality Preserving Projections.
Proceedings of the Neural Information Processing - 26th International Conference, 2019

Improved Multi-objective Evolutionary Subspace Clustering.
Proceedings of the Neural Information Processing - 26th International Conference, 2019

Fault Tolerant Photovoltaic Array: A Repair Circuit Based on Memristor Sensing.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Multi-objective Approach for Semi-Supervised Discriminant Analysis with Relative Distance.
Proceedings of the IEEE Congress on Evolutionary Computation, 2019

Online feature selection for multi-label classification in multi-objective optimization framework.
Proceedings of the ASONAM '19: International Conference on Advances in Social Networks Analysis and Mining, 2019

2018
A Differential Quantizer-Based Error Feedback Modulator for Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Differentially Quantized Bandpass Error Feedback Modulator for ADCs in Digital Radio.
Circuits Syst. Signal Process., 2018

A Hardware Accelerator for Convolutional Neural Network Using Fast Fourier Transform.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

An Improved Approach for EEG Signal Classification using Autoencoder.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

Supervised and Semi-supervised Multi-task Binary Classification.
Proceedings of the Neural Information Processing - 25th International Conference, 2018

Semi-supervised Transfer Metric Learning with Relative Constraints.
Proceedings of the Neural Information Processing - 25th International Conference, 2018

A Multi-kernel Semi-supervised Metric Learning Using Multi-objective Optimization Approach.
Proceedings of the Neural Information Processing - 25th International Conference, 2018

Multiobjective optimization based subspace clustering using evolvable genome structure.
Proceedings of the Genetic and Evolutionary Computation Conference Companion, 2018

Memristor based adaptive impedance and frequency tuning network.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

Two dimensional FFT architecture based on radix-4<sup>3</sup> algorithm with efficient output reordering.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

2017
Improved Multiple Faults-Aware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits.
IEEE Trans. Reliab., 2017

A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis.
IEEE Trans. Emerg. Top. Comput., 2017

Guest Editorial: Special Issue on "Secure and Fault-Tolerant Embedded Computing".
ACM Trans. Embed. Comput. Syst., 2017

Binary Decision Diagram Assisted Modeling of FPGA-Based Physically Unclonable Function by Genetic Programming.
IEEE Trans. Computers, 2017

Selected Articles from the IEEE ISED 2016 Conference.
J. Low Power Electron., 2017

An Optimal Leakage-Aware Approach for Nano-CMOS Post-Physical-Optimization.
J. Low Power Electron., 2017

Minimising Impact of Wire Resistance in Low-Power Crossbar Array Write Scheme.
J. Low Power Electron., 2017

An antenna selection scheme with MRE and AWC for decision fusion in cognitive radio.
Trans. Emerg. Telecommun. Technol., 2017

Reliable gas sensing with memristive array.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016
Fusion Rule for Cooperative Spectrum Sensing in Cognitive Radio.
Circuits Syst. Signal Process., 2016

A Novel Excess Sturdy-MASH-Loop-Delay Compensated Cross-Coupled Sigma-Delta Modulator.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Memristor Based Arbiter PUF: Cryptanalysis Threat and Its Mitigation.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Analytic models for crossbar read operation.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

2015
A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2<sup>m</sup>).
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Low-Cost Unified Design Methodology for Secure Test and Intellectual Property Core Protection.
IEEE Trans. Reliab., 2015

A Novel Memristor-Based Hardware Security Primitive.
ACM Trans. Embed. Comput. Syst., 2015

Selected Articles from the IEEE ISED 2014 Conference.
J. Low Power Electron., 2015

A Multiple Input Variable Output Switched Capacitor DC-DC Converter for Harnessing Renewable Energy and Powering LEDs.
J. Low Power Electron., 2015

A novel memristor based physically unclonable function.
Integr., 2015

2T2M memristor based TCAM cell for low power applications.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Fault detection and repair of DSC arrays through memristor sensing.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014
Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems.
J. Low Power Electron., 2014

A Novel Integrated Circuit Design Methodology Using Dynamic Library Concept with Reduced Non-Recurring Engineering Cost and Time-to-Market.
J. Low Power Electron., 2014

Selected Articles from the IEEE ISED 2013 Conference.
J. Low Power Electron., 2014

Energy Efficient Lifetime Reliability-Aware Checkpointing for Real-Time System.
J. Low Power Electron., 2014

TQCR-media access control: two-level quality of service provisioning media access control protocol for cognitive radio network.
IET Networks, 2014

Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis.
IEEE Embed. Syst. Lett., 2014

Write scheme for multiple Complementary Resistive Switch (CRS) cells.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Dual Extended Noise Shaping for High Performance Cross-Coupled Sigma-Delta Modulators.
Proceedings of the Eighth International Conference on Next Generation Mobile Apps, 2014

Spectrum Prediction in Cognitive Radio Networks: A Bayesian Approach.
Proceedings of the Eighth International Conference on Next Generation Mobile Apps, 2014

Diagnosis of SMGF in ESOP Based Reversible Logic Circuit.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

Using memristor state change behavior to identify faults in photovoltaic arrays.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Complementary resistive switch based stateful logic operations using material implication.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A low power and robust carbon nanotube 6T SRAM design with metallic tolerance.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Energy Aware Spectrum Decision Framework for Cognitive Radio Network: A Spectrum Decision Framework for Cognitive Radio Network with Energy Awareness.
J. Low Power Electron., 2013

Selected Articles from the IEEE ISED 2012 Conference.
J. Low Power Electron., 2013

Cellular Automata Approach for a Low Power Fusion Center to Evaluate Spectrum Status and Coverage Area in Cognitive Radios.
J. Low Power Electron., 2013

Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity.
Comput. Electr. Eng., 2013

Low Power and Robust Binary Tree SRAM Design for Embedded Systems.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

G-Let Based Authentication/Secret Message Transmission (GASMT).
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

A Novel Physical Synthesis Methodology in the VLSI Design Automation by Introducing Dynamic Library Concept.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

A Novel and Unified Digital IC Design and Automation Methodology with Reduced NRE Cost and Time-to-Market.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Multinomial Memristor Model for Simulations and Analysis.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Lifetime Reliability-Aware Checkpointing Mechanism: Modelling and Analysis.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Software Modification Aided Transient Error Tolerance for Embedded Systems.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A fast and Effective DFT for test and diagnosis of power switches in SoCs.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits.
J. Low Power Electron., 2012

VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Low complexity cross parity codes for multiple and random bit error correction.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

STEP: a unified design methodology for secure test and IP core protection.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
A Multi-Mode Sigma-Delta ADC for GSM/WCDMA/WLAN Applications.
J. Signal Process. Syst., 2011

Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Routing-Aware ILS Design Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.
J. Low Power Electron., 2011

Fault-tolerant de-Bruijn graph based multipurpose architecture and routing protocol for wireless sensor networks.
Int. J. Sens. Networks, 2011

Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN.
Circuits Syst. Signal Process., 2011

Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

BCH code based multiple bit error correction in finite field multiplier circuits.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits.
Proceedings of the International Symposium on Electronic System Design, 2011

MAC Protocol for Two Level QoS Support in Cognitive Radio Network.
Proceedings of the International Symposium on Electronic System Design, 2011

Single-Event Transient Analysis in High Speed Circuits.
Proceedings of the International Symposium on Electronic System Design, 2011

A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of GF(2<sup>m</sup>).
IEEE Trans. Very Large Scale Integr. Syst., 2010

Test Generation in Systolic Architecture for Multiplication Over GF(2 <sup>m</sup>).
IEEE Trans. Very Large Scale Integr. Syst., 2010

Simplified bit parallel systolic multipliers for special class of galois field (2<sup>m</sup>) with testability.
IET Comput. Digit. Tech., 2010

A Galois field-based logic synthesis with testability.
IET Comput. Digit. Tech., 2010

Secure Testable S-box Architecture for Cryptographic Hardware Implementation.
Comput. J., 2010

On the synthesis of attack tolerant cryptographic hardware.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Fault diagnosis in multi layered De Bruijn based architectures for sensor networks.
Proceedings of the Eigth Annual IEEE International Conference on Pervasive Computing and Communications, 2010

On the design of different concurrent EDC schemes for S-Box and GF(p).
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Layout-aware Illinois Scan design for high fault coverage coverage.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009
An O(m<sup>2</sup>)-depth quantum algorithm for the elliptic curve discrete logarithm problem over GF(2<sup>m</sup>)<sup>a</sup>.
Quantum Inf. Comput., 2009

Single error correctable bit parallel multipliers over GF(2<sup>m</sup>).
IET Comput. Digit. Tech., 2009

Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

C-testable S-box implementation for secure advanced encryption standard.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Single ended 6T SRAM with isolated read-port for low-power embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
C-testable bit parallel multipliers over <i>GF</i>(2<sup><i>m</i></sup>).
ACM Trans. Design Autom. Electr. Syst., 2008

GfXpress: A Technique for Synthesis and Optimization of GF(2<sup>m</sup>) Polynomials.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m).
IEEE Trans. Computers, 2008

Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation Specifications for Wireless Communication Receivers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

GA-based Optimization of Sigma-delta Modulators for Wireless Transceivers.
Eng. Lett., 2008

A Galois Field Based Logic Synthesis Approach with Testability.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Design of Reversible Finite Field Arithmetic Circuits with Error Detection.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Single Error Correcting Finite Field Multipliers Over GF(2m).
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography.
Proceedings of the Theory of Quantum Computation, 2008

Pseudo parallel architecture for AES with error correction.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Failure analysis for ultra low power nano-CMOS SRAM under process variations.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

ANFIS and NNARX based rainfall-runoff modeling.
Proceedings of the IEEE International Conference on Systems, 2008

GA-based optimization of a fourth-order sigma-delta modulator for WLAN.
Proceedings of the IEEE International Conference on Systems, 2008

A nano-CMOS process variation induced read failure tolerant SRAM cell.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Fault tolerant bit parallel finite field multipliers using LDPC codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Fault Tolerant Reversible Finite Field Arithmetic Circuits.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}).
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applications.
Proceedings of the 2007 IEEE International SOC Conference, 2007

SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Soft Error Mitigation in Switch Modules of SRAM-based FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

On the Hardware Reduction of z-Datapath of Vectoring CORDIC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Reliable network-on-chip based on generalized de Bruijn graph.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Single Event Upset Detection and Correction.
Proceedings of the 10th International Conference on Information Technology, 2007

A Triple-Mode Sigma-Delta Modulator Design for Wireless Standards.
Proceedings of the 10th International Conference on Information Technology, 2007

2006
An efficient technique for synthesis and optimization of polynomials in GF(2<sup><i>m</i></sup>).
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Easily Testable Implementation for Bit Parallel Multipliers in GF (2m).
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2002
Self-Checking 1-out-of-n CMOS Current-Mode Checker.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2000
An FIR digital filter using one-hot coded residue representation.
Proceedings of the 10th European Signal Processing Conference, 2000

1999
Residue-to-binary arithmetic converter for moduli set {2n -1, 2n, 2n+1, 2n+1 -1}.
Proceedings of the IEEE-EURASIP Workshop on Nonlinear Signal and Image Processing (NSIP'99), 1999

New area efficient residue-to-weighted number system converters.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999


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