Shanlin Xiao

Orcid: 0000-0002-1250-8704

According to our database¹, Shanlin Xiao authored at least 29 papers between 2016 and 2023.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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PhD thesis

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Links

On csauthors.net:

Bibliography

2023

SparseSpikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer.

[BibT_eX]

[DOI]

CoRR, 2023

Enabling energy-Efficient object detection with surrogate gradient descent in spiking neural networks.

[BibT_eX]

[DOI]

CoRR, 2023

Towards Energy-Efficient Asynchronous Circuit Design with Flip-Flop-to-Latch Replacement.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

Towards Efficient On-Chip Learning for Spiking Neural Networks Accelerator with Surrogate Gradient.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

2022

An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A dual-rail/single-rail hybrid system using null convention logic circuits.

[BibT_eX]

[DOI]

Microelectron. J., 2022

DFT Architecture for Click-Based Bundled-Data Asynchronous Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021

Balancing the Cost and Performance Trade-Offs in SNN Processors.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Data-Driven Asynchronous Neural Network Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Hand gesture recognition algorithm combining hand-type adaptive algorithm and effective-area ratio for efficient edge computing.

[BibT_eX]

[DOI]

J. Electronic Imaging, 2021

High-parallelism Inception-like Spiking Neural Networks for Unsupervised Feature Learning.

[BibT_eX]

[DOI]

Neurocomputing, 2021

Dimension fusion: Dimension-level dynamically composable accelerator for convolutional neural networks.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2021

High-Throughput Zipper Encoder for 800G Optical Communication System.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A high throughput spatially coupled low density generator matrix coding system.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

FWUA : A Flexible Winograd-Based Uniform Accelerator for 1D/2D/3D CNNs.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020

NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Low-Cost Adaptive Exponential Integrate-and-Fire Neuron Using Stochastic Computing.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2020

BioSNet: A Fast-Learning and High-Robustness Unsupervised Biomimetic Spiking Neural Network.

[BibT_eX]

[DOI]

CoRR, 2020

A Low-Cost and High-Throughput NoC-Aware Chip-to-Chip Interconnection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

A Low-Power Processing Element Based on Asynchronous Data-Driven Bit-Serial Multiplier for CNNs.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

An Asynchronous Convolution Process Engine forVGG-16 Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Pattern Recognition, 2020

2018

A Reconfigurable Process Engine for Flexible Convolutional Neural Network Acceleration.

[BibT_eX]

[DOI]

Xiaobai Chen

Shanlin Xiao

Zhiyi Yu

Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2018

2017

HOG-Based Object Detection Processor Design Using ASIP Methodology.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2016

An efficient embedded processor for object detection using ASIP methodology.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

Shanlin Xiao

Timeline

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