Xiangyu Meng

Orcid: 0000-0001-7956-8499

Affiliations:
  • The Hong Kong University of Science and Technology, Hong Kong
  • Sun Yat-Sen University, School of Electronics and Information Technology, Guangzhou, China


According to our database1, Xiangyu Meng authored at least 10 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

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Bibliography

2023
A 0.2-7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers.
IEEE Trans. Instrum. Meas., 2023

2021
Dimension fusion: Dimension-level dynamically composable accelerator for convolutional neural networks.
IEICE Electron. Express, 2021

A 1.8-GS/s 6-Bit Two-Step SAR ADC in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020
A 28-GHz 16-Gb/s High Efficiency 16-QAM Transmitter in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 0.5-5 GHz 0.3-mW 50% duty-cycle corrector in 65-nm CMOS.
Proceedings of the 2020 IEEE Region 10 Conference, 2020

W-Band Synthesized Modulator and Demodulator with Wideband Performance in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A Fully Integrated 150-GHz Transceiver Front-End in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 28-GHz Compact SPDT Switch Using LC-Based Spiral Transmission Lines in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A 16-GB/S 0-DB Power Back-Off 16-QAM Transmitter at 28 GHZ in 65-NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018


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