Tsuyoshi Isshiki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., January, 2024

2023

Text-Independent Speaker Recognition System Using Feature-Level Fusion for Audio Databases of Various Sizes.

[BibT_eX]

[DOI]

Neha Chauhan

SN Comput. Sci., September, 2023

LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure.

[BibT_eX]

[DOI]

Tamon Sadasue

IPSJ Trans. Syst. LSI Des. Methodol., 2023

2022

Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework.

[BibT_eX]

[DOI]

Eiji Yoshiya

Tomoya Nakanishi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022

2021

Scalable Hardware Architecture for fast Gradient Boosted Tree Training.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2021

RTL Design Framework for Embedded Processor by using C++ Description.

[BibT_eX]

[DOI]

Eiji Yoshiya

Tomoya Nakanishi

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Scalable Full Hardware Logic Architecture for Gradient Boosted Tree Training.

[BibT_eX]

[DOI]

Tamon Sadasue

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019

Pipeline Segmentation using Level-Set Method.

[BibT_eX]

[DOI]

Thitiporn Chanwimaluang

P. Hoonsuwan

Proceedings of the 2019 IEEE International Geoscience and Remote Sensing Symposium, 2019

Speaker Recognition Using LPC, MFCC, ZCR Features with ANN and SVM Classifier for Large Input Database.

[BibT_eX]

[DOI]

Neha Chauhan

Proceedings of the IEEE 4th International Conference on Computer and Communication Systems, 2019

2017

An Accurate and Fast Trace-aware Performance Estimation Model For Prioritized MPSoC Bus With Multiple Interfering Bus-Masters.

[BibT_eX]

[DOI]

Farhan Shafiq

Mohammad Zalfany Urfianto

IPSJ Trans. Syst. LSI Des. Methodol., 2017

Hybrid shared-memory and message-passing multiprocessor system-on-chip for UWB MAC layer.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2017

HOG-Based Object Detection Processor Design Using ASIP Methodology.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Narrow Fingerprint Template Synthesis by Clustering Minutiae Descriptors.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2017

Hybrid Minutiae Descriptor for Narrow Fingerprint Verification.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2017

2016

Efficient Synchronization for Distributed Embedded Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Fast Trace Aware Statistical Based Prediction Model with Burst Traffic Modeling for Contention Stall in A Priority Based MPSoC Bus.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2016

An efficient embedded processor for object detection using ASIP methodology.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015

Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension.

[BibT_eX]

[DOI]

J. Inf. Process., 2015

Efficient Design Exploration Framework of SW/HW Systems Based on Tightly-coupled Thread Model.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2015

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Online Detection of Spoof Fingers for Smartphone-Based Applications.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2014

A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach.

[BibT_eX]

[DOI]

J. Inf. Process., 2014

Retargeting Derivative-ASIP with Assembly Converter Tool.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

Distributed synchronization for message-passing based embedded multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

Dalvik bytecode acceleration using Fetch/Decode Hardware Extension with hybrid Execution.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Custom instruction search for application specific instruction-set processor using guided simulated annealing.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing.

[BibT_eX]

[DOI]

J. Inf. Process., 2013

A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

2012

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2012

A Low-Cost and Energy-Efficient Multiprocessor System-on-Chip for UWB MAC Layer.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2012

Narrow Fingerprint Sensor Verification with Template Updating Technique.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Application-specific Instruction-Set Processor design methodology for wireless image transmission systems.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

Robust Multiple Minutiae Partitions for Fingerprint Authentication.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Symposium on Biometrics and Security Technologies, 2012

A Reconfigurable High Performance ASIP Engine for Image Signal Processing.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

A MRF-Based approach for a multisensor land cover mapping of mis-resgistered images.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Geoscience and Remote Sensing Symposium, 2012

Hybrid shared-memory and message-passing multiprocessor system-on-chip for UWB MAC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2012

A reconfigurable ASIP-based approach for high performance image signal processing.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Unique Fingerprint-Image-Generation Algorithm for Line Sensors.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Practical Orientation Field Estimation for Embedded Fingerprint Recognition Systems.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2011

2010

A Unified Performance Estimation Method for Hardware and Software Components in Multiprocessor System-On-Chips.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2010

Orientation Field Estimation for Embedded Fingerprint Authentication System.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2010

Ultra fast fingerprint indexing for embedded system.

[BibT_eX]

[DOI]

Proceedings of the Second International Conference of Soft Computing and Pattern Recognition, 2010

Cool MPSoC programming.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

A novel similarity measurement for minutiae-based fingerprint verification.

[BibT_eX]

[DOI]

Proceedings of the Fourth IEEE International Conference on Biometrics: Theory Applications and Systems, 2010

2009

Entropy Decoding Processor for Modern Multimedia Applications.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Trace-driven workload simulation method for Multiprocessor System-On-Chips.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Decomposition of Task-Level Concurrency on C Programs Applied to the Design of Multiprocessor SoC.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A Multiprocessor SoC Architecture with Efficient Communication Infrastructure and Advanced Compiler Support for Easy Application Development.

[BibT_eX]

[DOI]

Mohammad Zalfany Urfianto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

MAPS: an integrated framework for MPSoC application parallelization.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

H.264/AVC decoder SoC towards the low cost mobile video player.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International SOC Conference, 2007

2005

A Fingerprint Matching Using Minutia Ridge Shape for Low Cost Match-on-Card Systems.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

2002

New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Realization of fingerprint identification module on DSP board.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

High density bit-serial FPGA with LUT embedding shift register function.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

A new methodology for low delay real-time videophone software architecture design.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Efficient method for face region quality enhancement in low bit rate video coding.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

H.263+ Video Encoder/Decoder LSI Featuring System-MSPA Architecture and Improved Rate Control Method.

[BibT_eX]

Proceedings of the World Multiconference on Systemics, Cybernetics and Informatics, 2001

2000

Cost-effective shadowing method using the ED-buffer on an adaptive light cube.

[BibT_eX]

[DOI]

Makoto Ishikawa

Vis. Comput., 2000

1999

Efficient anti-aliasing algorithm for computer generated images.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998

A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract).

[BibT_eX]

[DOI]

Takenobu Shimizugashira

Akihisa Ohta

Imanuddin Amril

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

New FPGA Architecture for Bit-Serial Pipeline Datapath.

[BibT_eX]

[DOI]

Akihisa Ohta

Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

FPGA for High-Performance Bit-Serial Pipeline Datapath.

[BibT_eX]

[DOI]

Takenobu Shimizugashira

Akihisa Ohta

Imanuddin Amril

Proceedings of the ASP-DAC '98, 1998

1997

Bit-serial pipeline synthesis and layout for large-scale configurable systems.

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Bit-serial pipeline synthesis for multi-FPGA systems with C++ design capture.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996

1995

High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994

Hight-Performance Datapath Implementation on Field-Programmable Multi-Chip Module (FPMCM).

[BibT_eX]

[DOI]