Gi-Joon Nam

According to our database1, Gi-Joon Nam authored at least 69 papers between 1999 and 2020.

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Bibliography

2020
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.
CoRR, 2020

BISTLock: Efficient IP Piracy Protection using BIST.
Proceedings of the IEEE International Test Conference, 2020

DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Routing-Free Crosstalk Prediction.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Self-Aligned Double-Patterning Aware Legalization.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Latch Clustering for Timing-Power Co-Optimization.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Integrated Latch Placement and Cloning for Timing Optimization.
ACM Trans. Design Autom. Electr. Syst., 2019

Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing.
Proceedings of the 2019 International Symposium on Physical Design, 2019

2018
OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Guest Editors' Introduction: Hardware Accelerators for Data Centers.
IEEE Des. Test, 2018

DATC RDF: An Open Design Flow from Logic Synthesis to Detailed Routing.
CoRR, 2018

End-to-End Industrial Study of Retiming.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Interconnect Optimization Considering Multiple Critical Paths.
Proceedings of the 2018 International Symposium on Physical Design, 2018

DATC RDF: an academic flow from logic synthesis to detailed routing.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator.
Proc. VLDB Endow., 2017

DATC RDF: Robust design flow database: Invited paper.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
OWARU: free space-aware timing-driven incremental placement.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

OpenDesign flow database: the infrastructure for VLSI design and design automation research.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Feature detection for image analytics via FPGA acceleration.
IBM J. Res. Dev., 2015

Toward Metrics of Design Automation Research Impact.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
New Algorithmic Techniques for Complex EDA Problems.
VLSI Design, 2014

Opportunities in power distribution network system optimization: from EDA perspective.
Proceedings of the International Symposium on Physical Design, 2014

Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Applying VLSI EDA to energy distribution system design.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Wire delay variability in nanoscale technology and its impact on physical design.
Proceedings of the International Symposium on Quality Electronic Design, 2013

2012
An accurate sparse-matrix based framework for statistical static timing analysis.
Integr., 2012

Placement: Hot or Not?
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Guiding a physical design closure system to produce easier-to-route designs with more predictable timing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Physical Synthesis with Clock-Network Optimization for Large Systems on Chips.
IEEE Micro, 2011

Floorplanning challenges in early chip planning.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

The ISPD-2011 routability-driven placement contest and benchmark suite.
Proceedings of the 2011 International Symposium on Physical Design, 2011

Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
Guest Editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

ITOP: integrating timing optimization within placement.
Proceedings of the 2010 International Symposium on Physical Design, 2010

What makes a design difficult to route.
Proceedings of the 2010 International Symposium on Physical Design, 2010

New placement prediction and mitigation techniques for local routing congestion.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Design-hierarchy aware mixed-size placement for routability optimization.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Detecting tangled logic structures in VLSI netlists.
Proceedings of the 47th Design Automation Conference, 2010

2009
Ispd2009 clock network synthesis contest.
Proceedings of the 2009 International Symposium on Physical Design, 2009

CRISP: Congestion reduction by iterated spreading during placement.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
Placement.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Guest Editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

The ISPD global routing benchmark suite.
Proceedings of the 2008 International Symposium on Physical Design, 2008

2007
Diffusion-Based Placement Migration With Application on Legalization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Techniques for Fast Physical Synthesis.
Proc. IEEE, 2007

The nuts and bolts of physical synthesis.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

ISPD placement contest updates and ISPD 2007 global routing contest.
Proceedings of the 2007 International Symposium on Physical Design, 2007

RQL: Global Placement via Relaxed Quadratic Spreading and Linearization.
Proceedings of the 44th Design Automation Conference, 2007

Performance modeling for early analysis of multi-core systems.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Hippocrates: First-Do-No-Harm Detailed Placement.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

ISPD 2005/2006 Placement Benchmarks.
Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006
A Fast Hierarchical Quadratic Placement Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

ISPD 2006 Placement Contest: Benchmark Suite and Results.
Proceedings of the 2006 International Symposium on Physical Design, 2006

2005
Two-dimensional position detection system with MEMS accelerometers, readout circuitry, and microprocessor for padless mouse applications.
IEEE Trans. Very Large Scale Integr. Syst., 2005

The ISPD2005 placement contest and benchmark suite.
Proceedings of the 2005 International Symposium on Physical Design, 2005

A semi-persistent clustering technique for VLSI circuit placement.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Placement stability metrics.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints.
IEEE Trans. Computers, 2004

2003
Effective free space management for cut-based placement via analytical constraint generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2002
A new FPGA detailed routing approach via search-based Booleansatisfiability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Free space management for cut-based placement.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
A boolean satisfiability-based incremental rerouting approach with application to FPGAs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Two-Dimensional Position Detection System with MEMS Accelerometer for MOUSE Applications.
Proceedings of the 38th Design Automation Conference, 2001

1999
Satisfiability-Based Detailed FPGA Routing.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999


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