Shayan Zhang

According to our database1, Shayan Zhang authored at least 4 papers between 1994 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

1994
A delay model and optimization method of a low-power BiCMOS logic circuit.
IEEE J. Solid State Circuits, October, 1994

Analysis of the switching speed of BiCMOS buffer under high current.
IEEE J. Solid State Circuits, July, 1994

Analysis of BiCMOS buffer for input voltages with finite rise time.
IEEE J. Solid State Circuits, July, 1994


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