Jonathan Chang

According to our database1, Jonathan Chang authored at least 47 papers between 1996 and 2018.

Collaborative distances:
  • Dijkstra number2 of two.
  • Erdős number3 of three.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Joint Label Inference in Networks.
Proceedings of the Companion of the The Web Conference 2018 on The Web Conference 2018, 2018

A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Session 11 overview: SRAM: Memory subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
Joint Label Inference in Networks.
Journal of Machine Learning Research, 2017

Learning Representations of Emotional Speech with Deep Convolutional Generative Adversarial Networks.
CoRR, 2017

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

EE5: When will we stop driving our cars?
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Learning representations of emotional speech with deep convolutional generative adversarial networks.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

2016
A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Highlights of the IEEE ISSCC 2014 Processors, Digital, Memory, Biomedical & Next-Generation Systems Technologies, and Imagers, MEMS, Medical & Displays Sessions.
J. Solid-State Circuits, 2015

A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications.
J. Solid-State Circuits, 2015

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

F2: Memory trends: From big data to wearable devices.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Product-level reliability estimator with budget-based reliability management in 20nm technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
Joint Inference of Multiple Label Types in Large Networks.
CoRR, 2014

Learning a Concept Hierarchy from Multi-labeled Documents.
Proceedings of the Advances in Neural Information Processing Systems 27: Annual Conference on Neural Information Processing Systems 2014, 2014

The importance of DFX, a foundry perspective.
Proceedings of the 2014 International Test Conference, 2014

Joint Inference of Multiple Label Types in Large Networks.
Proceedings of the 31th International Conference on Machine Learning, 2014

A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC2RA) circuitry achieving 3x reduction on speed variation for single ended arrays.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
Location3: How Users Share and Respond to Location-Based Data on Social.
Proceedings of the Fifth International Conference on Weblogs and Social Media, 2011

2010
A 45 nm 8-Core Enterprise Xeon¯ Processor.
J. Solid-State Circuits, 2010

Erratum: SGDQN is Less Careful than Expected.
Journal of Machine Learning Research, 2010

Not-So-Latent Dirichlet Allocation: Collapsed Gibbs Sampling Using Human Judgments.
Proceedings of the 2010 Workshop on Creating Speech and Language Data with Amazon's Mechanical Turk, 2010

A 1.2 TB/s on-chip ring interconnect for 45nm 8-core enterprise Xeon® processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

ePluribus: Ethnicity on Social Networks.
Proceedings of the Fourth International Conference on Weblogs and Social Media, 2010

Gesture Recognition in the Haptic Creature.
Proceedings of the Haptics: Generating and Perceiving Tangible Sensations, 2010

2009
Relational Topic Models for Document Networks.
Proceedings of the Twelfth International Conference on Artificial Intelligence and Statistics, 2009

Comparison of child-human and child-computer interactions based on manual annotations.
Proceedings of the Second Workshop on Child, Computer and Interaction, 2009

Reading Tea Leaves: How Humans Interpret Topic Models.
Proceedings of the Advances in Neural Information Processing Systems 22: 23rd Annual Conference on Neural Information Processing Systems 2009. Proceedings of a meeting held 7-10 December 2009, 2009

Connections between the lines: augmenting social networks with text.
Proceedings of the 15th ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, Paris, France, June 28, 2009

A 45nm 8-core enterprise Xeon® processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007
Automatic Instruction-Level Software-Only Recovery.
IEEE Micro, 2007

UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development.
Computer Architecture Letters, 2007

PU-BCD: Exponential Family Models for the Coarse- and Fine-Grained All-Words Tasks.
Proceedings of the 4th International Workshop on Semantic Evaluations, 2007

2006
Automatic Instruction-Level Software-Only Recovery.
Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN 2006), 2006

Selective Runtime Memory Disambiguation in a Dynamic Binary Translator.
Proceedings of the Compiler Construction, 15th International Conference, 2006

2005
Software-controlled fault tolerance.
TACO, 2005

Design and Evaluation of Hybrid Fault-Detection Systems.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

SWIFT: Software Implemented Fault Tolerance.
Proceedings of the 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 2005

2004
RIFLE: An Architectural Framework for User-Centric Information-Flow Security.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

2003
The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

1996
Analysis and Detection of Timing Failures in an Experimental Test Chip.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996


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