Sheng Lin

According to our database, Sheng Lin authored at least 7 papers between 2008 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors.

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi

IEEE Trans. Very Large Scale Integr. Syst., 2011

Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset.

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010

Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability.

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi

Integr., 2010

Read-out schemes for a CNTFET-based crossbar memory.

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

Soft-Error Hardening Designs of Nanoscale CMOS Latches.

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

A Novel Hardened Design of a CMOS Memory Cell at 32nm.

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

A low leakage 9t sram cell for ultra-low power operation.

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008