Yong-Bin Kim

According to our database1, Yong-Bin Kim authored at least 114 papers between 1997 and 2018.

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Bibliography

2018
Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme.
Integration, 2018

Area Efficient 4Gb/s Clock Data Recovery Using Improved Phase Interpolator with Error Monitor.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Low Power Digital Temperature Sensor Using Modified Inverter Interlaced Cascaded Delay Cell.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Generalized Adaptive Variable Bit Truncation Method for Approximate Stochastic Computing.
Proceedings of the International SoC Design Conference, 2018

Low-Power Null Convention Logic Multiplier Design Based On Gate Diffusion Input Technique.
Proceedings of the International SoC Design Conference, 2018

2017
A Two-Parameter Calibration Technique Tracking Temperature Variations for Current Source Mismatch.
IEEE Trans. on Circuits and Systems, 2017

Fully Integrated on-Chip Switched DC-DC Converter for Battery-Powered Mixed-Signal SoCs.
Symmetry, 2017

Variable bit truncation technique for approximate stochastic computing (ASC).
Proceedings of the International SoC Design Conference, 2017

Low-power null convention logic design based on modified gate diffusion input technique.
Proceedings of the International SoC Design Conference, 2017

A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1st speculative tap.
Proceedings of the International SoC Design Conference, 2017

Time-domain temperature sensor based on interlaced hysteresis delay cells.
Proceedings of the International SoC Design Conference, 2017

A 4Gb/s half-rate DFE with switched-cap and IIR summation for data correction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Switched Capacitor and Infinite Impulse Response Summation for a Quarter-Rate DFE with 4Gb/s Data Rate.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories.
IEEE Trans. Computers, 2016

An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data Correction.
Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016

A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration.
Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016

Approximate stochastic computing (ASC) for image processing applications.
Proceedings of the International SoC Design Conference, 2016

Parallel decoding for multi-stage BCH decoder.
Proceedings of the International SoC Design Conference, 2016

Hybrid GDI-NCL for area/power reduction.
Proceedings of the International SoC Design Conference, 2016

Integrated circuits design using carbon nanotube field effect transistor.
Proceedings of the International SoC Design Conference, 2016

Current mode four-quadrant multiplier design using CNTFET.
Proceedings of the International SoC Design Conference, 2016

A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface between DRAM and AP/SoC.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier.
IEEE Trans. on Circuits and Systems, 2015

2014
Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches.
IEEE Trans. VLSI Syst., 2014

Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance.
J. Electrical and Computer Engineering, 2014

A low power high resolution digital PWM with process and temperature calibrations for digital controlled DC-DC converters.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

An area efficient low power high speed S-Box implementation using power-gated PLA.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A novel mixed-signal self-calibration technique for baseband filters in systems-on-chip mobile transceivers.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2012
A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA Transmitter.
IEEE Trans. Industrial Electronics, 2012

Design and analysis of the quadfferential amplifier.
Microelectronics Journal, 2012

A design and integration of Parametric Measurement Unit on to a 600MHz DCL.
Proceedings of the International SoC Design Conference, 2012

A low stand-by power start-up circuit for SMPS PWM controller.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

A fully integrated switched-capacitor DC-DC converter with dual output for low power application.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Hardening a memory cell for low power operation by gate leakage reduction.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors.
IEEE Trans. VLSI Syst., 2011

A design approach of a Parametric Measurement Unit on to a 600MHz DCL.
Proceedings of the International SoC Design Conference, 2011

Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010
A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops.
VLSI Design, 2010

Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems.
IEEE Trans. Instrumentation and Measurement, 2010

Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability.
Integration, 2010

High speed and low power transceiver design with CNFET and CNT bundle interconnect.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A CMOS low-power low-offset and high-speed fully dynamic latched comparator.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A 65nm CMOS ultra low power and low noise 131M front-end transimpedance amplifier.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Read-out schemes for a CNTFET-based crossbar memory.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

8Gb/s capacitive low power and high speed 4-PWAM transceiver design.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

A low-offset high-speed double-tail dual-rail dynamic latched comparator.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Performance assessment of analog circuits with carbon nanotube FET (CNFET).
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Modelling a CNTFET with Undeposited CNT Defects.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems.
IEEE Trans. VLSI Syst., 2009

A Novel Statistical Timing and Leakage Power Characterization of Partially Depleted Silicon-on-Insulator Gates.
IEEE Trans. Instrumentation and Measurement, 2009

Guest Editorial.
J. Electronic Testing, 2009

Soft-Error Hardening Designs of Nanoscale CMOS Latches.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Errors in DNA Self-Assembly by Synthesized Tile Sets.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

A Novel Hardened Design of a CMOS Memory Cell at 32nm.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels.
IEEE Trans. Industrial Informatics, 2008

Standby power reduction using optimal supply voltage and body-bias voltage.
IEICE Electronic Express, 2008

Monomer Control for Error Tolerance in DNA Self-Assembly.
J. Electronic Testing, 2008

A low power 32 nanometer CMOS digitally controlled oscillator.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Low power 8T SRAM using 32nm independent gate FinFET technology.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

A low leakage 9t sram cell for ultra-low power operation.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Checkpointing of Rectilinear Growth in DNA Self-Assembly.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
ProSight PTM 2.0: improved protein identification and characterization for top down mass spectrometry.
Nucleic Acids Research, 2007

Low power CMOS electronic central pattern generator design for a biomimetic underwater robot.
Neurocomputing, 2007

Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology.
IEICE Electronic Express, 2007

Leakage Minimization Technique for Nanoscale CMOS VLSI.
IEEE Design & Test of Computers, 2007

A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Optimal Body Biasing for Minimum Leakage Power in Standby Mode.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Fault Tolerant Source Routing for Network-on-Chip.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine.
IEEE Trans. VLSI Syst., 2006

Measuring the timing jitter of ATE in the frequency domain.
IEEE Trans. Instrumentation and Measurement, 2006

Evaluating the Yield of Repairable SRAMs for ATE.
IEEE Trans. Instrumentation and Measurement, 2006

Design metal-dot based QCA circuits using SPICE model.
Microelectronics Journal, 2006

A Novel 8-Phase PLL Design for PWM Scheme in High Speed I/O Circuits.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

PWAM signalling scheme for high speed serial link transceiver design.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Error Tolerance of DNA Self-Assembly by Monomer Concentration Control.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
Environmental-based characterization of SoC-based instrumentation systems for stratified testing.
IEEE Trans. Instrumentation and Measurement, 2005

ASLIC: A Low Power CMOS Analog Circuit Design Automation.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

QCA-based nano circuits design [adder design example].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Quantum-dot cellular automata SPICE macro model.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Data Dependent Jitter (DDJ) Characterization Methodology.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

On the Modeling and Analysis of Jitter in ATE Using Matlab.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004
ProSight PTM: an integrated environment for protein identification and characterization by top-down mass spectrometry.
Nucleic Acids Research, 2004

Fast and accurate DAC modeling techniques based on wavelet theory.
Microelectronics Journal, 2004

Balanced dual-stage repair for dependable embedded memory cores.
Journal of Systems Architecture, 2004

SRAM word-oriented redundancy methodology using built in self-repair.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Low power real time electronic neuron VLSI design using subthreshold technique.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A fast and precise interconnect capacitive coupling noise model.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

SET-based nano-circuit simulation and design method using HSPICE.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Reliability Modeling and Assurance of Clockless Wave Pipeline.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Scan Test of IP Cores in an ATE Environment.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Fault tolerant clockless wave pipeline design.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
Analysis and measurement of timing jitter induced by radiated EMI noise in automatic test equipment.
IEEE Trans. Instrumentation and Measurement, 2003

Automating Wave-Pipelined Circuit Design.
IEEE Design & Test of Computers, 2003

Guest Editors' Introduction: Clockless VLSI Systems.
IEEE Design & Test of Computers, 2003

Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems.
Proceedings of the 2nd IEEE International Symposium on Network Computing and Applications (NCA 2003), 2003

Optimal Spare Utilization in Repairable and Reliable Memory Cores.
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

Need For Undergraduate And Graduate-Level Education In Testing Of Microelectronic Circuits And Systems.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

A Novel Clocking Strategy for Dynamic Circuits.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

A novel 32-bit scalable multiplier architecture.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
Hardware/Software Co-Reliability of Configurable Digital Systems.
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

Design flow of robust routed power distribution for low power ASIC.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A Test-Vector Generation Methodology for Crosstalk Noise Faults.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS.
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001

1997
A CMOS delayed locked loop (DLL) for reducing clock skew to under 500 ps.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997


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