Yong-Bin Kim
Orcid: 0000-0002-7014-5630
According to our database1,
Yong-Bin Kim
authored at least 155 papers
between 1997 and 2023.
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Bibliography
2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the 20th International SoC Design Conference, 2023
2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
2021
A Stray-Insensitive Low-Power Capacitive Sensor Interface with Time-Compensation Technique.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the International SoC Design Conference, 2020
An Ultra-Low-Power Tunable Bump Circuit using Source-Degenerated Differential Transconductor.
Proceedings of the International SoC Design Conference, 2020
Proceedings of the International SoC Design Conference, 2020
2019
10 GHz Standing Wave Oscillator Based Clock Distribution Network Considering Distributed Capacitance.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
Standing Wave Oscillator Based Clock Distribution Minimizing Equivalent Capacitance for Process and Temperature variation.
Proceedings of the 2019 International SoC Design Conference, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
2018
Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme.
Integr., 2018
Area Efficient 4Gb/s Clock Data Recovery Using Improved Phase Interpolator with Error Monitor.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Low Power Digital Temperature Sensor Using Modified Inverter Interlaced Cascaded Delay Cell.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Generalized Adaptive Variable Bit Truncation Method for Approximate Stochastic Computing.
Proceedings of the International SoC Design Conference, 2018
Low-Power Null Convention Logic Multiplier Design Based On Gate Diffusion Input Technique.
Proceedings of the International SoC Design Conference, 2018
2017
A Two-Parameter Calibration Technique Tracking Temperature Variations for Current Source Mismatch.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Fully Integrated on-Chip Switched DC-DC Converter for Battery-Powered Mixed-Signal SoCs.
Symmetry, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the International SoC Design Conference, 2017
Low-power null convention logic design based on modified gate diffusion input technique.
Proceedings of the International SoC Design Conference, 2017
A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1<sup>st</sup> speculative tap.
Proceedings of the International SoC Design Conference, 2017
Proceedings of the International SoC Design Conference, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Switched Capacitor and Infinite Impulse Response Summation for a Quarter-Rate DFE with 4Gb/s Data Rate.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
2016
A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories.
IEEE Trans. Computers, 2016
An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data Correction.
Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016
A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration.
Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International SoC Design Conference, 2016
A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface between DRAM and AP/SoC.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
2015
Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A process tolerant semi-self impedance calibration method for LPDDR4 memory controller.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
A 10-Gb/s receiver with a continuous-time linear equalizer and 1-tap decision-feedback equalizer.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
2014
Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance.
J. Electr. Comput. Eng., 2014
Calibration technique tracking temperature for current-steering digital-to-analog converters.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Full custom implementation of a S-Box circuit architecture using power gated PLA structure.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
A built-in calibration system to optimize third-order intermodulation performance of RF amplifiers.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
A low power high resolution digital PWM with process and temperature calibrations for digital controlled DC-DC converters.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
A novel mixed-signal self-calibration technique for baseband filters in systems-on-chip mobile transceivers.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
A high performance modulo 2<sup>n</sup>+1 squarer design based on carbon nanotube technology.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
A switched-capacitor DC-DC converter using delta-sigma digital pulse frequency modulation control method.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
2012
IEEE Trans. Ind. Electron., 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
A high speed low power modulo 2<sup>n</sup>+1 multiplier design using carbon-nanotube technology.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Low power, high PVT variation tolerant central pattern generator design for a bio-hybrid micro robot.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Design and evaluation of Side Channel Attack resistant asynchronous AES Round Function.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
All-digital phased-locked loop with local passive interpolation time-to-digital converter based on a tristate inverter.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the International SoC Design Conference, 2012
Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
A fully integrated switched-capacitor DC-DC converter with dual output for low power application.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Proceedings of the International SoC Design Conference, 2011
Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
2010
VLSI Design, 2010
IEEE Trans. Instrum. Meas., 2010
Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability.
Integr., 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
2009
A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2009
A Novel Statistical Timing and Leakage Power Characterization of Partially Depleted Silicon-on-Insulator Gates.
IEEE Trans. Instrum. Meas., 2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
2008
IEEE Trans. Ind. Informatics, 2008
IEICE Electron. Express, 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
2007
ProSight PTM 2.0: improved protein identification and characterization for top down mass spectrometry.
Nucleic Acids Res., 2007
Low power CMOS electronic central pattern generator design for a biomimetic underwater robot.
Neurocomputing, 2007
IEICE Electron. Express, 2007
A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
2006
A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine.
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Instrum. Meas., 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
2005
Environmental-based characterization of SoC-based instrumentation systems for stratified testing.
IEEE Trans. Instrum. Meas., 2005
Microelectron. J., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
2004
ProSight PTM: an integrated environment for protein identification and characterization by top-down mass spectrometry.
Nucleic Acids Res., 2004
Microelectron. J., 2004
IEEE J. Solid State Circuits, 2004
J. Syst. Archit., 2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Low power real time electronic neuron VLSI design using subthreshold technique.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A fast and precise interconnect capacitive coupling noise model.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004
Proceedings of the First Conference on Computing Frontiers, 2004
2003
Analysis and measurement of timing jitter induced by radiated EMI noise in automatic test equipment.
IEEE Trans. Instrum. Meas., 2003
Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems.
Proceedings of the 2nd IEEE International Symposium on Network Computing and Applications (NCA 2003), 2003
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003
Need For Undergraduate And Graduate-Level Education In Testing Of Microelectronic Circuits And Systems.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
2001
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001
1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997