Shigeru Oyanagi

According to our database, Shigeru Oyanagi authored at least 26 papers between 1977 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Underwater-Drone With Panoramic Camera for Automatic Fish Recognition Based on Deep Learning.

Lin Meng, Takuma Hirayama, Shigeru Oyanagi

IEEE Access, 2018

2017

The Development of Underwater-Drone equipped with 360-degree Panorama Camera in Opensource Hardware.

Lin Meng, Takuma Hirayama, Shigeru Oyanagi

Proceedings of the 2017 International Conference on Identification, 2017

2013

A Real-Time Burst Analysis Method.

Ryohei Ebina, Kenji Nakamura, Shigeru Oyanagi

Int. J. Artif. Intell. Tools, 2013

2012

Performance Evaluation of Treecode Algorithm for N-Body Simulation Using GridRPC System

Truong Vinh Truong Duy, Katsuhiro Yamazaki, Shigeru Oyanagi

CoRR, 2012

Hybrid MPI-OpenMP Paradigm on SMP Clusters: MPEG-2 Encoder and N-Body Simulation

Truong Vinh Truong Duy, Katsuhiro Yamazaki, Kosai Ikegami, Shigeru Oyanagi

CoRR, 2012

2011

A Real-Time Burst Detection Method.

Ryohei Ebina, Kenji Nakamura, Shigeru Oyanagi

Proceedings of the IEEE 23rd International Conference on Tools with Artificial Intelligence, 2011

An Input Buffer Architecture for On-chip Routers.

Chu Van Thiem, Shigeru Oyanagi

Proceedings of the Second International Conference on Networking and Computing, 2011

An Improvement of Router Throughput for On-Chip Networks Using On-the-fly Virtual Channel Allocation.

Son Truong Nguyen, Shigeru Oyanagi

Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011

2010

The Design of On-the-Fly Virtual Channel Allocation for Low Cost High Performance On-Chip Routers.

Son Truong Nguyen, Shigeru Oyanagi

Proceedings of the First International Conference on Networking and Computing, 2010

Control Independence Using Dual Renaming.

Lin Meng, Shigeru Oyanagi

Proceedings of the First International Conference on Networking and Computing, 2010

A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip Networks.

Son Truong Nguyen, Shigeru Oyanagi

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate.

Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi

IEICE Trans. Inf. Syst., 2009

2008

Three-stage pipeline implementation for SHA2 using data forwarding.

Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi

Proceedings of the FPL 2008, 2008

Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding.

Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi

Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

2006

Mining the K-Most Interesting Frequent Patterns Sequentially.

Quang Tran Minh, Shigeru Oyanagi, Katsuhiro Yamazaki

Proceedings of the Intelligent Data Engineering and Automated Learning, 2006

ExMiner: An Efficient Algorithm for Mining Top-K Frequent Patterns.

Quang Tran Minh, Shigeru Oyanagi, Katsuhiro Yamazaki

Proceedings of the Advanced Data Mining and Applications, Second International Conference, 2006

2004

Speculative Selection Routing in 2D Torus Network.

Tran Cong So, Shigeru Oyanagi, Katsuhiro Yamazaki

IEICE Trans. Inf. Syst., 2004

2002

Mining WWW Access Sequence by Matrix Clustering.

Shigeru Oyanagi, Kazuto Kubota, Akihiko Nakase

Proceedings of the WEBKDD 2002, 2002

2001

Implementation and performance evaluation of dynamic scheduling for parallel decision tree generation.

Kazuto Kubota, Akihiko Nakase, Shigeru Oyanagi

Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

1996

Improving the performance of global communication on a three-dimensional torus network.

Yasushi Kawakura, Noboru Tanabe, Shigeru Oyanagi

Syst. Comput. Jpn., 1996

1994

Improving the Performance of Global Communication on a 3D torus network.

Yasushi Kawakura, Shigeru Oyanagi

Proceedings of the 1994 International Conference on Parallel Processing, 1994

1992

Implementation of the prodigy parallel AI machine and performance evaluation of communication.

Noboru Tanabe, Sadao Nakamura, Takashi Suzuoka, Shigeru Oyanagi

Syst. Comput. Jpn., 1992

1991

Base-m n-cube: High Performance Interconnection Networks for Highly Parallel Computer PRODIGY.

Noboru Tanabe, Takashi Suzuoka, Sadao Nakamura, Yasushi Kawakura, Shigeru Oyanagi

Proceedings of the International Conference on Parallel Processing, 1991

1989

Network Performance of the Prodigy Parallel AI Machine.

Takashi Suzuoka, Noboru Tanabe, Sadao Nakamura, Sumikazu Fujita, Shigeru Oyanagi

Syst. Comput. Jpn., 1989

1980

A Dynamically Microprogammable Computer with Low-Level Parallelism.

Hiroshi Hagiwara, Shinji Tomita, Shigeru Oyanagi, Kiyoshi Shibayama

IEEE Trans. Computers, 1980

1977

Hardware Organization of a Low Level Parallel Processor.

Shinji Tomita, Kiyoshi Shibayama, Shigeru Oyanagi, Hiroshi Hagiwara

Proceedings of the Information Processing, 1977