Shinji Tomita
According to our database1,
Shinji Tomita
authored at least 44 papers
between 1971 and 2018.
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Bibliography
2018
2012
Prototype Implementation of a GPU-based Interactive Coupled Fluid-Structure Simulation.
Proceedings of the 13th ACIS International Conference on Software Engineering, 2012
2011
A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth.
J. Comput. Sci. Technol., 2011
2008
A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases.
IEICE Trans. Inf. Syst., 2008
Proceedings of the IEEE Virtual Reality Conference 2008 (VR 2008), 2008
Interactive Fluid Simulation and its Remote Steering Framework with Visual and Haptic Feedback.
Proceedings of the 2008 International Conference on Modeling, 2008
Low-Complexity Bypass Network Using Small RAM.
Proceedings of the 2008 International Conference on Computer Design, 2008
2007
SIGARCH Comput. Archit. News, 2007
2006
Spatial analysis of centralization and decentralization in the population migration network.
Proceedings of the Asia-Pacific Symposium on Information Visualisation, 2006
2005
Program Phase Detection Based Dynamic Control Mechanisms for Pipeline Stage Unification Adoption.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005
2004
Implementation of Cell-Projection Parallel Volume Rendering with Dynamic Load Balancing.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004
Simulating realistic force and shape of virtual cloth with adaptive meshes and its parallel implementation in OpenMP.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2004
Proceedings of the New Frontiers in Artificial Intelligence - JSAI 2003 and JSAI 2004 Conferences and Workshops, Niigata, Japan, June 23-27, 2003 and Kanazawa, Japan, May 31, 2004
2003
Proceedings of the Multi-Agent-Based Simulation III, 4th International Workshop, 2003
A Web-Based Education Tool for Collaborative Learning of Assembly Programming.
Proceedings of the IADIS International Conference WWW/Internet 2003, 2003
2002
Proceedings of the International Conference on Computers in Education, 2002
2001
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001
1999
A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR.
Int. J. Parallel Program., 1999
1998
Optimized Code Generation for Heterogeneous Computing Environment using Parallelizing Compiler TINPAR.
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998
1997
Exploiting Parallel Computers to Reduce Neural Network Training Time of Real Applications.
Proceedings of the High Performance Computing, International Symposium, 1997
Proceedings of the 2nd International Workshop on Parallel Symbolic Computation, 1997
Efficient Goal Scheduling in Concurrent Logic Language using Type-Based Dependency Analysis.
Proceedings of the Advances in Computing Science, 1997
1996
Proceedings of the 10th international conference on Supercomputing, 1996
1995
Proceedings of the 9th international conference on Supercomputing, 1995
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995
Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995
1993
Proceedings of the Proceedings Supercomputing '93, 1993
1992
Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture.
Proceedings of the 6th international conference on Supercomputing, 1992
1991
DSNS (dynamically-hazard-resolved statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture.
SIGARCH Comput. Archit. News, 1991
Toward advanced parallel processing: exploiting parallelism at task and instruction levels.
IEEE Micro, 1991
1989
Syst. Comput. Jpn., 1989
SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989
The Kyushu University Reconfigurable Parallel Processor - Design Philosophy and Architecture.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989
The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures.
Proceedings of the 3rd international conference on Supercomputing, 1989
1988
SIGARCH Comput. Archit. News, 1988
1986
A Computer with Low-Level Parallelism QA-2: Its Applications to 3-D Graphics and Prolog/Lisp Machines.
Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986
ISDN and X25 - Response.
Proceedings of the Information Processing 86, 1986
1984
Proceedings of the 11th Annual Conference on Computer Graphics and Interactive Techniques, 1984
1983
Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, 1983
1980
IEEE Trans. Computers, 1980
Performance evaluation and improvement of a dynamically microprogrammable computer with low-level parallelism.
Proceedings of the 13th annual workshop on Microprogramming, 1980
Performance Evaluation and Improvement of a Dynamically Microprogrammable Computer with Low-Level Parallelism.
Proceedings of the Information Processing, Proceedings of the 8th IFIP Congress 1980, Tokyo, Japan - October 6-9, 1980 and Melbourne, Australia, 1980
1977
Hardware Organization of a Low Level Parallel Processor.
Proceedings of the Information Processing, 1977
1971
On-Line, Real-Time, Multiple-Speech Output System.
Proceedings of the Information Processing, Proceedings of IFIP Congress 1971, Volume 1, 1971