Shinpei Kayano

According to our database, Shinpei Kayano authored at least 5 papers between 1988 and 1995.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1995

A novel memory cell for multiport RAM on 0.5 μm CMOS Sea-of-Gates.

Koji Nii, Hideshi Maeno, Tokuya Osawa, Shuhei Iwade, Shinpei Kayano, Hiroshi Shibata

IEEE J. Solid State Circuits, March, 1995

1994

A high-density data-path generator with stretchable cells.

Yoshiki Tsujihashi, Hisashi Matsumoto, Hidekatsu Nishimaki, Atsushi Miyanishi, Hiroomi Nakao, Osamu Kitada, Shuhei Iwade, Shinpei Kayano, Masayoshi Sakao

IEEE J. Solid State Circuits, January, 1994

1991

A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture.

Yutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Hiromi Notani, Harufusa Kondoh, Shinpei Kayano

IEEE J. Solid State Circuits, November, 1991

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing.

Yasunobu Nakase, Kakutaro Suda, Koichiro Mashiko, Tatsuhiko Ikeda, Shinpei Kayano

IEEE J. Solid State Circuits, April, 1991

1988

A macro analysis of soft errors in static RAMs.

Yasunobu Nakase, Kenji Anami, Tohru Shiomi, Atsushi Ohba, Shinpei Kayano

IEEE J. Solid State Circuits, April, 1988