Koichiro Mashiko

According to our database, Koichiro Mashiko authored at least 18 papers between 1985 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Evaluation of SRAM PUF Characteristics and Generation of Stable Bits for IoT Security.

Pyi Phyo Aung, Koichiro Mashiko, Nordinah Binti Ismail, Chia Yee Ooi

Proceedings of the Emerging Trends in Intelligent Computing and Informatics, 2019

2007

A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm.

Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada

IEICE Trans. Electron., 2007

2006

High-Speed Continuous-Time Subsampling Bandpass DeltaSigmaAD Modulator Architecture Employing Radio Frequency DAC.

Masafumi Uemori, Haruo Kobayashi, Tomonari Ichikawa, Atsushi Wada, Koichiro Mashiko, Toshiro Tsukada, Masao Hotta

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout.

Hao San, Akira Hayakawa, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Kazuyuki Kobayashi, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

2000

A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology.

Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2000

1997

Authors Reply.

Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko

IEEE J. Solid State Circuits, 1997

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply].

Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi

IEEE J. Solid State Circuits, 1997

A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme.

Hiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, Hisanori Hamano

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996

A 64-bit carry look ahead adder using pass transistor BiCMOS gates.

Kiniio Ueda, Hiroaki Suzuki, Kakutaro Suda, Hirofumi Shinohara, Koichiro Mashiko

IEEE J. Solid State Circuits, 1996

A fully compensated active pull-down ECL circuit with self-adjusting driving capability.

Kimio Ueda, Nagisa Sasaki, Hisayasu Sato, Koichiro Mashiko

IEEE J. Solid State Circuits, 1996

Leading-zero anticipatory logic for high-speed floating point addition.

Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi

IEEE J. Solid State Circuits, 1996

A 1.9-GHz single chip IF transceiver for digital cordless phones.

Hisayasu Sato, Kenichi Kashiwagi, Kazuhito Niwano, Tetsuya Iga, Tatsuhiko Ikeda, Koichiro Mashiko, Tadashi Sumi, Koji Tsuchihashi

IEEE J. Solid State Circuits, 1996

A 286 MHz 64-b floating point multiplier with enhanced CG operation.

Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi

IEEE J. Solid State Circuits, 1996

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture.

Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko

IEEE J. Solid State Circuits, 1996

How to design low-power digital cellular phones.

Koichiro Mashiko

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995

A BiCMOS wired-OR logic.

Yasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko

IEEE J. Solid State Circuits, June, 1995

1994

A voltage compensated series-gate bipolar circuit operating at sub-2 V.

Hisayasu Sato, Kimio Ueda, Nagisa Sasaki, Tatsuhiko Ikeda, Koichiro Mashiko

IEEE J. Solid State Circuits, October, 1994

1985

Test Pattern Considerations for Fault Tolerant High Density DRAM.

Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, T. Nakano

Proceedings of the Proceedings International Test Conference 1985, 1985