Shireesh Verma

According to our database, Shireesh Verma authored at least 12 papers between 2005 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

<i>A Special Issue on</i> Low Power Design and Verification Techniques.

Shireesh Verma

J. Low Power Electron., 2011

Power Management Design and Verification.

Bhanu Kapoor, Shireesh Verma

J. Low Power Electron., 2011

2009

Impact of SoC power management techniques on verification and testing.

Bhanu Kapoor, Shankar Hemmady, Shireesh Verma, Kaushik Roy, Manuel A. d'Abreu

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

Tutorial: SoC Power Management Verification and Testing Issues.

Bhanu Kapoor, J. Marc Edwards, Shankar Hemmady, Shireesh Verma, Kaushik Roy

Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008

Panel: Software practices for verification/testbench management.

Shireesh Verma, Srinath Atluri, Valeria Bertacco, Mark Glasser, Badri Gopalan, Sharon Rosenberg

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

Evaluation of an efficient control-oriented coverage metric.

Kiran Ramineni, Shireesh Verma, Ian G. Harris

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

Panel: SoC power management implications on validation and testing.

Bhanu Kapoor, John Goodenough, Shankar Hemmady, Shireesh Verma, Manuel A. d'Abreu, Kaushik Roy

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

2007

Automatic generation of functional coverage models from CTL.

Shireesh Verma, Ian G. Harris, Kiran Ramineni

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Improving feasible interactions among multiple processes.

Kiran Ramineni, Ian G. Harris, Shireesh Verma

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions.

Shireesh Verma, Ian G. Harris, Kiran Ramineni

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Error Detection Using Model Checking vs. Simulation.

Shireesh Verma, Patricia S. Lee, Ian G. Harris

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005

An efficient control-oriented coverage metric.

Shireesh Verma, Kiran Ramineni, Ian G. Harris

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005