Valeria Bertacco

According to our database1, Valeria Bertacco authored at least 147 papers between 1996 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2017, "For contributions to computer-aided verification and reliable system design".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
Collaborative Accelerators for Streamlining MapReduce on Scale-up Machines With Incremental Data Aggregation.
IEEE Trans. Computers, 2020

Neksus: An Interconnect for Heterogeneous System-In-Package Architectures.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020

Thwarting Control Plane Attacks with Displaced and Dilated Address Spaces.
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

GraphVine: Exploiting Multicast for Scalable Graph Analytics.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Seesaw: End-to-end Dynamic Sensing for IoT using Machine Learning.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Centaur: Hybrid Processing in On/Off-chip Memory Architecture for Graph Analytics.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
MessageFusion: On-path Message Coalescing for Energy Efficient and Scalable Graph Analytics.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

SiPterposer: A Fault-Tolerant Substrate for Flexible System-in-Package Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

DREDGE: Dynamic Repartitioning during Dynamic Graph Execution.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

Collaborative accelerators for in-memory MapReduce on scale-up machines.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Heterogeneous Memory Subsystem for Natural Graph Analytics.
Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018

Low-Overhead Microarchitectural Patching for Multicore Memory Subsystems.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

SWAN: mitigating hardware trojans with design ambiguity.
Proceedings of the International Conference on Computer-Aided Design, 2018

Vulnerability-tolerant secure architectures.
Proceedings of the International Conference on Computer-Aided Design, 2018

Symbolic assertion mining for security validation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
SNIFFER: A high-accuracy malware detector for enterprise-based systems.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Regaining Lost Cycles with HotCalls: A Fast Interface for SGX Secure Enclaves.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

MTraceCheck: Validating Non-Deterministic Behavior of Memory Consistency Models in Post-Silicon Validation.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

3DFAR: A three-dimensional fabric for reliable multi-core processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

DOVE: pinpointing firmware security vulnerabilities via symbolic control flow assertion mining (work-in-progress).
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

AGARSoC: Automated test and coverage-model generation for verification of accelerator-rich SoCs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Energy efficient object detection on the mobile GP-GPU.
Proceedings of the IEEE AFRICON 2017, Cape Town, South Africa, September 18-20, 2017, 2017

2016
Resource Conscious Diagnosis and Reconfiguration for NoC Permanent Faults.
IEEE Trans. Computers, 2016

BugMD: automatic mismatch diagnosis for bug triaging.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Correct runtime operation for NoCs through adaptive-region protection.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Post-Silicon Validation of Multiprocessor Memory Consistency.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Panel: When will the cost of dependability end innovation in computer design?
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Highly Fault-tolerant NoC Routing with Application-aware Congestion Management.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

NoCVision: A Network-on-Chip Dynamic Visualization Solution.
Proceedings of the 8th International Workshop on Network on Chip Architectures, 2015

ReDEEM: A heterogeneous distributed microarchitecture for energy-efficient reliability.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

ItHELPS: Iterative high-accuracy error localization in post-silicon.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014
ForEVeR: A complementary formal and runtime verification approach to correct NoC functionality.
ACM Trans. Embed. Comput. Syst., 2014

Post-silicon platform for the functional diagnosis and debug of networks-on-chip.
ACM Trans. Embed. Comput. Syst., 2014

Cardio: CMP Adaptation for Reliability Through Dynamic Introspective Operation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs.
IEEE Trans. Computers, 2014

DiAMOND: Distributed alteration of messages for on-chip network debug.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

High-radix on-chip networks with low-radix routers.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Brisk and limited-impact NoC routing reconfiguration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

ArChiVED: Architectural checking via event digests for high performance validation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Power-Aware NoCs through Routing and Topology Reconfiguration.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Cobra: A comprehensive bundle-based reliable architecture.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

uDIREC: unified diagnosis and reconfiguration for frugal bypass of NoC faults.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Machine learning-based anomaly detection for post-silicon bug diagnosis.
Proceedings of the Design, Automation and Test in Europe, 2013

On the use of GP-GPUs for accelerating compute-intensive EDA applications.
Proceedings of the Design, Automation and Test in Europe, 2013

Schnauzer: scalable profiling for likely security bug sites.
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

2012
A Reliable Routing Architecture and Algorithm for NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Comprehensive online defect diagnosis in on-chip networks.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Architectural Trace-Based Functional Coverage for Multiprocessor Verification.
Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012

Viper: Virtual pipelines for enhanced reliability.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Bridging pre- and post-silicon debugging with BiPeD.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Functional post-silicon diagnosis and debug for networks-on-chip.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Approximating checkers for simulation acceleration.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

SAGA: SystemC acceleration on GPU architectures.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Checking architectural outputs instruction-by-instruction on acceleration platforms.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Humans for EDA and EDA for humans.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

SystemC simulation on GP-GPUs: CUDA vs. OpenCL.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Gate-Level Simulation with GPU Computing.
ACM Trans. Design Autom. Electr. Syst., 2011

A distributed and topology-agnostic approach for on-line NoC testing.
Proceedings of the NOCS 2011, 2011

Formally enhanced runtime verification to ensure NoC functional correctness.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Functional correctness for CMP interconnects.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Post-silicon bug diagnosis with inconsistent executions.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Simulation-based signal selection for state restoration in silicon debug.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Cardio: Adaptive CMPs for reliability through dynamic introspective operation.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

ReliNoC: A reliable network for priority-based on-chip communication.
Proceedings of the Design, Automation and Test in Europe, 2011

DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips.
Proceedings of the 48th Design Automation Conference, 2011

Highly scalable distributed dataflow analysis.
Proceedings of the CGO 2011, 2011

ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Logic synthesis and circuit customization using extensive external don't-cares.
ACM Trans. Design Autom. Electr. Syst., 2010

SoCGuard: A runtime verification solution for the functional correctness of SoCs.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

EQUIPE: Parallel equivalence checking with GP-GPUs.
Proceedings of the 28th International Conference on Computer Design, 2010

Application-Aware diagnosis of runtime hardware faults.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Verification Failures: What to Do When Things Go Wrong.
Proceedings of the Hardware and Software: Verification and Testing, 2010

Fault-based attack of RSA authentication.
Proceedings of the Design, Automation and Test in Europe, 2010

Bridging pre-silicon verification and post-silicon validation.
Proceedings of the 47th Design Automation Conference, 2010

Electronic design automation for social networks.
Proceedings of the 47th Design Automation Conference, 2010

Post-silicon debugging for multi-core designs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Functional Design Errors in Digital Circuits - Diagnosis, Correction and Repair
Lecture Notes in Electrical Engineering 32, Springer, ISBN: 978-1-4020-9364-7, 2009

Inferno: Streamlining Verification With Inferred Semantics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A Flexible Software-Based Framework for Online Detection of Hardware Defects.
IEEE Trans. Computers, 2009

Incremental Verification with Error Detection, Diagnosis, and Visualization.
IEEE Des. Test Comput., 2009

Dacota: Post-silicon validation of the memory subsystem in multi-core designs.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Activity-based refinement for abstraction-guided simulation.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Caspar: Hardware patching for multicore processors.
Proceedings of the Design, Automation and Test in Europe, 2009

A highly resilient routing algorithm for fault-tolerant NoCs.
Proceedings of the Design, Automation and Test in Europe, 2009

GCS: High-performance gate-level simulation with GPGPUs.
Proceedings of the Design, Automation and Test in Europe, 2009

Customizing IP cores for system-on-chip designs using extensive external don't-cares.
Proceedings of the Design, Automation and Test in Europe, 2009

09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers.
Proceedings of the Algorithms and Applications for Next Generation SAT Solvers, 08.11., 2009

Vicis: a reliable network for unreliable silicon.
Proceedings of the 46th Design Automation Conference, 2009

Human computing for EDA.
Proceedings of the 46th Design Automation Conference, 2009

Event-driven gate-level simulation with GP-GPUs.
Proceedings of the 46th Design Automation Conference, 2009

Debugging strategies for mere mortals.
Proceedings of the 46th Design Automation Conference, 2009

2008
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Fixing Design Errors With Counterexamples and Resynthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

SafeResynth: A new technique for physical synthesis.
Integr., 2008

Reliable Systems on Unreliable Fabrics.
IEEE Des. Test Comput., 2008

Automating Postsilicon Debugging and Repair.
Computer, 2008

Testudo: Heavyweight security analysis via statistical sampling.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Optimizing non-monotonic interconnect using functional simulation and logic restructuring.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Reap what you sow: spare cells for post-silicon metal fix.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Reversi: Post-silicon validation system for modern microprocessors.
Proceedings of the 26th International Conference on Computer Design, 2008

CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework.
Proceedings of the 26th International Conference on Computer Design, 2008

Post-silicon verification for cache coherence.
Proceedings of the 26th International Conference on Computer Design, 2008

Panel: Software practices for verification/testbench management.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

MCjammer: Adaptive Verification for Multi-core Designs.
Proceedings of the Design, Automation and Test in Europe, 2008

Random Stimulus Generation using Entropy and XOR Constraints.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Postplacement rewiring by exhaustive search for functional symmetries.
ACM Trans. Design Autom. Electr. Syst., 2007

Microprocessor Verification via Feedback-Adjusted Markov Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Simulation-Based Bug Trace Minimization With BMC-Based Refinement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Architecting a reliable CMP switch architecture.
ACM Trans. Archit. Code Optim., 2007

Chico: An On-chip Hardware Checker for Pipeline Control Logic.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Automating post-silicon debugging and repair.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Automatic error diagnosis and correction for RTL designs.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Engineering trust with semantic guardians.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Low-cost protection for SER upsets and silicon defects.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Node Mergers in the Presence of Don't Cares.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Safe Delay Optimization for Physical Synthesis.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Low maintenance verification.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Formal verification for real-world designs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Verification through the principle of least astonishment.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

BulletProof: a defect-tolerant CMP switch architecture.
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

Distance-Guided Hybrid Verification with GUIDO.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Distance-guided hybrid verification with GUIDO.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Shielding against design flaws with field repairable control logic.
Proceedings of the 43rd Design Automation Conference, 2006

Ultra low-cost defect protection for microprocessor pipelines.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

Depth-driven verification of simultaneous interfaces.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Scalable Hardware Verification with Symbolic Simulation.
Springer, ISBN: 978-0-387-24411-2, 2006

2005
Deployment of Better Than Worst-Case Design: Solutions and Needs.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Post-placement rewiring and rebuffering by exhaustive search for functional symmetries.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

StressTest: an automatic approach to test generation via activity monitors.
Proceedings of the 42nd Design Automation Conference, 2005

STACCATO: disjoint support decompositions from BDDs through symbolic kernels.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Opportunities and challenges for better than worst-case design.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Microarchitectural power modeling techniques for deep sub-micron microprocessors.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Circuit-aware architectural simulation.
Proceedings of the 41th Design Automation Conference, 2004

2002
Efficient state representation for symbolic simulation.
Proceedings of the 39th Design Automation Conference, 2002

2000
Smart Simulation Using Collaborative Formal and Simulation Engines.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999
Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits.
Proceedings of the 36th Conference on Design Automation, 1999

1997
The disjunctive decomposition of logic functions.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996
Boolean Function Representation Based on Disjoint-Support Decompositions.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Boolean Function Representation Using Parallel-Access Diagrams.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996


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