Shoujun Wang

Orcid: 0000-0001-5284-3796

According to our database1, Shoujun Wang authored at least 20 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A Novel Boundary-Guided Global Feature Fusion Module for Instance Segmentation.
Neural Process. Lett., April, 2024

AF-FPN: an attention-guided enhanced feature pyramid network for breakwater armor layer unit segmentation.
Multim. Syst., February, 2024

2021
Design and test of large-range wave height sensor based on water resistance measurement and fuzzy system.
Pers. Ubiquitous Comput., 2021

Super-resolution of Pneumocystis carinii pneumonia CT via self-attention GAN.
Comput. Methods Programs Biomed., 2021

2020
Semiparametric Deep Learning Manipulator Inverse Dynamics Modeling Method for Smart City and Industrial Applications.
Complex., 2020

Deep Learning Aided Dynamic Parameter Identification of 6-DOF Robot Manipulators.
IEEE Access, 2020

2019
Modeling and Simulation of Robot Inverse Dynamics Using LSTM-Based Deep Learning Algorithm for Smart Cities and Factories.
IEEE Access, 2019

Visual Servoing of Magnetic Swimming Robot Based on Mean Shift and Fast Template Matching Algorithm.
Proceedings of the 2019 IEEE International Conference on Robotics and Biomimetics, 2019

Swimming Characteristics of Soft robot with Magnetoelastic Material.
Proceedings of the 2019 IEEE International Conference on Robotics and Biomimetics, 2019

2018
Kinematics and Transmission Performance Analyses of a 2T2R Type 4-DOF Spatial Parallel Manipulator.
J. Robotics, 2018

2017
Research and Development of Ball-Picking Robot Technology.
Proceedings of the Intelligent Robotics and Applications - 10th International Conference, 2017

2016
A platform design of networked service in industrial robot welding.
Proceedings of the 9th International Congress on Image and Signal Processing, 2016

2008
A 0.18-µm CMOS clock and data recovery circuit with reference-less dual loops.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2006
A 0.18µm CMOS clock and data recovery circuit with extended operation range.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations.
Proceedings of the 43rd Design Automation Conference, 2006

A 0.18µm CMOS Receiver with Decision-feedback Equalization for Backplane Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data Communications.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

A 0.18µm CMOS transceiver design for high-speed backplane data communications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design considerations for 2nd-order and 3rd-order bang-bang CDR loops.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technology.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005


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