William Bereza

According to our database, William Bereza authored at least 7 papers between 2005 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2009

Nonlinear behavior study in digital bang-bang PLL.

Albert Vareljian, Mohsen Moussavi, William Bereza, Walter Fergusson, Charles E. Berndt, Rakesh H. Patel

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2007

Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A.

Walter Fergusson, Rakesh H. Patel, William Bereza

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Evolving into Embedded Develop.

Matt Fletcher, William Bereza, Mike Karlesky, Greg Williams

Proceedings of the AGILE 2007 Conference (AGILE 2007), 2007

2006

PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations.

William Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel

Proceedings of the 43rd Design Automation Conference, 2006

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs.

Rakesh H. Patel, William Bereza

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

Design considerations for 2nd-order and 3rd-order bang-bang CDR loops.

Shoujun Wang, Haitao Mei, Mashkoor Baig, William Bereza, Tadeusz Kwasniewski, Rakesh H. Patel

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A signal integrity-based link performance simulation platform.

Yuming Tao, William Bereza, Rakesh H. Patel, Sergey Y. Shumarayev, Tad A. Kwasniewski

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005