Shrestha Bansal

Orcid: 0000-0002-4818-3366

According to our database1, Shrestha Bansal authored at least 5 papers between 2017 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2021
Neural-Network Based Self-Initializing Algorithm for Multi-Parameter Optimization of High-Speed ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
10.8 A 4-Element 500MHz-Modulated-BW 40mW 6b 1GS/s Analog-Time-to-Digital-Converter-Enabled Spatial Signal Processor in 65nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A 2Vpk-pk, diff Input Range 1GS/s Voltage-to-Time Converter with Tunable Distortion Compensation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2017
Digital LDO with analog-assisted dynamic reference correction for fast and accurate load regulation.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Energy Efficient NoC Router for High Throughput Applications in Many-Core GPUs.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017


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