# Subhanshu Gupta

According to our database

Collaborative distances:

^{1}, Subhanshu Gupta authored at least 25 papers between 2005 and 2020.Collaborative distances:

## Timeline

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Book In proceedings Article PhD thesis Other## Links

#### On csauthors.net:

## Bibliography

2020

IEEE Trans. Circuits Syst., 2020

Low-Latency Reconfigurable Entropy Digital True Random Number Generator With Bias Detection and Correction.

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Proceedings of the 21st IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2020

10.8 A 4-Element 500MHz-Modulated-BW 40mW 6b 1GS/s Analog-Time-to-Digital-Converter-Enabled Spatial Signal Processor in 65nm CMOS.

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

From Battery Enabled to Natural Harvesting: Enzymatic BioFuel Cell Assisted Integrated Analog Front-End in 130nm CMOS for Long-Term Monitoring.

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

An Integrated Discrete-Time Delay-Compensating Technique for Large-Array Beamformers.

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 25.6μW 8.97ps Period Jitter Phase-Locked Relaxation Oscillator with sub-1µS Start-Up for Low-Power IoT.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Energy-Efficient Serialized Walsh-Hadamard Transform Based Feature-Extraction for Information-Aware Compressive Sensing.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 3.51µW 0.31µVrms Biofuel Cell Enabled Integrated Analog CMOS Front-End in 130 nm CMOS.

Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017

Frequency-Channelized Mismatch-Shaped Quadrature Data Converters for Carrier Aggregation in MU-MIMO LTE-A.

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A compressive sensing information aware analog front end for IoT sensors using adaptive clocking techniques.

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016

A highly linear 4GS/s uncalibrated voltage-to-time converter with wide input range.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Lomb algorithm versus fast fourier transform in heart rate variability analyses of pain in premature infants.

Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

Synchronous multi-signal acquisition for WBSNs using gold-code based joint-compressive sensing.

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

2014

IEEE J. Solid State Circuits, 2014

2012

J. Signal Process. Syst., 2012

A 0.8-2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass ΣΔ ADC in 0.13 µm CMOS.

IEEE J. Solid State Circuits, 2012

2011

Multi-rate polyphase DSP and LMS calibration schemes for oversampled data conversion systems.

Proceedings of the IEEE International Conference on Acoustics, 2011

2010

A Mode-I/Mode-III UWB LNA with programmable gain and 20 dB WLAN blocker rejection in 130nm CMOS.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2008

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Hybrid modeling techniques for low OSR cascade continuous-time SigmaDelta modulators.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

A Digital-Summing Feedforward Sigma-Delta Modulator and its Application to a Cascade ADC.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005