Eiichi Goto

According to our database1, Eiichi Goto authored at least 34 papers between 1959 and 1995.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

1995
Fast Evaluation of the Elementary Functions in Single Precision.
IEEE Trans. Computers, 1995

Evaluation of the Hitachi S-3800 Supercomputer Using Six Benchmarks.
Int. J. High Perform. Comput. Appl., 1995

1994
QFP wiring problem-introduction and analytical considerations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers.
IEEE Trans. Computers, 1994

A Simulation Study on the Interactions between Multithreaded Architectures and the Cache.
Int. J. High Speed Comput., 1994

Fast Evaluation of the Elementary Functions in Double Precision.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1992
Evaluation of range-checking addressing modes and the architecture of FLATS2.
Syst. Comput. Jpn., 1992

Evaluation of the continuation bit in the Cyclic Pipeline Computer.
Parallel Comput., 1992

1991
Pseudorandom Rounding for Truncated Multipliers.
IEEE Trans. Computers, 1991

Effects of Multiple Instruction Stream Execution on Cache Performance.
Int. J. High Speed Comput., 1991

Josephson Supercomputer Design Using Quantum Flux Parametron.
Int. J. High Speed Comput., 1991

Quantum Flux Parametron - A Single Quantum Flux Superconducting Logic Device
Studies in Josephson Supercomputers 2, WorldScientific, ISBN: 978-981-4506-52-6, 1991

1990
Multiple instruction streams in a highly pipelined processor.
Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990

1989
CPC (Cyclic Pipeline Computer) - An Architecture Suited for Josephson and Pipelined-Memory Machines.
IEEE Trans. Computers, 1989

A note on the preconditioning for factorization of homogeneous polynomials.
SIGSAM Bull., 1989

Run-Time Checking in Lisp by Integrating Memory Addressing and Range Checking.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

1986
DC Flux Parametron - A New Approach to Josephson Junction Logic
World Scientific Series in Computer Science 6, World Scientific, ISBN: 978-981-4513-64-7, 1986

1984
Circuit Simulation Code Generation by Computer Algebra.
Proceedings of the RIMS Symposia on Software Science and Engineering II, 1984

1982
Design of a Lisp Machine - FLATS.
Proceedings of the 1982 ACM Symposium on LISP and Functional Programming, 1982

1979
FLATS, a Machine for Numerical, Symbolic and Associative Computing.
Proceedings of the 6th Annual Symposium on Computer Architecture, 1979

1978
Genetic Order and Compactifying Garbage Collectors.
Inf. Process. Lett., 1978

Electron beam lithography for advanced LSl fabrication.
Proceedings of the American Federation of Information Processing Societies: 1978 National Computer Conference, 1978

1977
"V-Tape", A Virtual Memory Oriented Data Type, and its Resource Requirements.
Inf. Process. Lett., 1977

An O(N) Algorithm for Finding Periodicity of a Sequence Using Hash Coding.
Inf. Process. Lett., 1977

Parallel Hashing Algorithms.
Inf. Process. Lett., 1977

Performance of Parallel Hash Hardware with Key Deletion.
Proceedings of the Information Processing, 1977

1976
A Hashing Method for Fast Set Operations.
Inf. Process. Lett., 1976

Hashing LEMMAs on time complexities with applications to formula manipulation.
Proceedings of the third ACM Symposium on Symbolic and Algebraic Manipulation, 1976

1971
An Efficient Bit Table Technique for Dynamic Storage Allocation of 2<sup>n</sup>-word Blocks.
Commun. ACM, 1971

1968
Memory systems.
Proceedings of the Information Processing, Proceedings of IFIP Congress 1968, Edinburgh, UK, 5-10 August 1968, Volume 2, 1968

1964
A Note on Logical Gain.
IEEE Trans. Electron. Comput., 1964

1962
Some Theorems Useful in Threshold Logic for Enumerating Boolean Functions.
Proceedings of the Information Processing, Proceedings of the 2nd IFIP Congress 1962, Munich, Germany, August 27, 1962

1960
Esaki Diode High-Speed Logical Circuits.
IRE Trans. Electron. Comput., 1960

1959
Application of error-correcting codes to multi-way switching.
Proceedings of the Information Processing, 1959


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