Shujiang Ji

Orcid: 0000-0002-5442-092X

According to our database1, Shujiang Ji authored at least 5 papers between 2020 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL.
IEEE J. Solid State Circuits, 2023

2022
A Highly Integrated Passive Wireless Sensing System With Synchronized Data Streaming of Multiple Tags.
IEEE Internet Things J., 2022

2021
A novel method to improve the subcarrier frequency accuracy for UHF RFID sensing system.
Proceedings of the IEEE International Conference on RFID, 2021

A 7.9-14.3GHz -243.3dB FoMT Sub-Sampling PLL with Transformer-Based Dual-Mode VCO in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
A Novel Charge Pump with Ultra-Low Current Mismatch and Variation for PLL.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020


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