Shuu'ichirou Yamamoto
According to our database1,
Shuu'ichirou Yamamoto
authored at least 9 papers
between 2009 and 2021.
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Bibliography
2021
Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches.
IEEE Open J. Circuits Syst., 2021
2020
Proactive useless data flush architecture for nonvolatile SRAM using magnetic tunnel junctions.
IEICE Electron. Express, 2020
2018
Design and Performance of Virtually Nonvolatile Retention Flip-Flop Using Dual-Mode Inverters.
Proceedings of the 2018 New Generation of CAS, 2018
2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2015
Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Comparative study of power-gating architectures for nonvolatile SRAM cells based on spintronics technology.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Monolithic integration of pseudo-spin-MOSFETs using a custom CMOS chip fabricated through multi-project wafer service.
Proceedings of the European Solid-State Device Research Conference, 2013
2009
Nonvolatile SRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009