Yusuke Shuto

According to our database, Yusuke Shuto authored at least 10 papers between 2009 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2021

Analog In-memory Computing in FeFET-based 1T1R Array for Edge AI Applications.

D. Saito, T. Kobayashi, Hiroki Koga, Nicolo Ronchi, Kaustuv Banerjee, Yusuke Shuto, Jun Okuno, Kenta Konishi, Luca Di Piazza, Arindam Mallik, Jan Van Houdt, Masanori Tsukamoto, K. Ohkuri, Taku Umebayashi, Takayuki Ezaki

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

High-Endurance and Low-Voltage operation of 1T1C FeRAM Arrays for Nonvolatile Memory Application.

Jun Okuno, Takafumi Kunihiro, Kenta Konishi, Hideki Maemura, Yusuke Shuto, Fumitaka Sugaya, Monica Materano, Tarek Ali, Maximilian Lederer, Kati Kühnel, Konrad Seidel, Uwe Schroeder, Thomas Mikolajick, Masanori Tsukamoto, Taku Umebayashi

Proceedings of the IEEE International Memory Workshop, 2021

2018

A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops.

Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami

Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application.

Kimiyoshi Usami, Junya Akaike, Sosuke Akiba, Masaru Kudo, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami

Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

2016

Design and implementation of nonvolatile power-gating SRAM using SOTB technology.

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Energy performance of nonvolatile power-gating SRAM using SOTB technology.

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

2015

Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology.

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Comparative study of power-gating architectures for nonvolatile SRAM cells based on spintronics technology.

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Monolithic integration of pseudo-spin-MOSFETs using a custom CMOS chip fabricated through multi-project wafer service.

Ryosho Nakane, Yusuke Shuto, Hiroaki Sukegawa, Zhenchao Wen, Shuu'ichirou Yamamoto, Seiji Mitani, Masaaki Tanaka, Koichiro Inomata, Satoshi Sugahara

Proceedings of the European Solid-State Device Research Conference, 2013

2009

Nonvolatile SRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices.

Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009