Shyamapada Mukherjee

According to our database, Shyamapada Mukherjee authored at least 17 papers between 2013 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

An extract-then-abstract based method to generate disaster-news headlines using a DNN extractor followed by a transformer abstractor.

Sumanta Banerjee, Shyamapada Mukherjee, Sivaji Bandyopadhyay, Partha Pakray

Inf. Process. Manag., May, 2023

PHetDP: A Placement Algorithm for Heterogeneous FPGAs with Delayed Packing.

Sharbani Purkayastha, Shyamapada Mukherjee

Circuits Syst. Signal Process., February, 2023

2022

Congestion-Aware Rectilinear Steiner Tree Construction Using PB-SAT.

Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee

J. Circuits Syst. Comput., 2022

A Reward-based Framework for Recovery and Utilization of Recyclable Wastes using Blockchain.

Yagnyasenee Sen Gupta, Shyamapada Mukherjee

Proceedings of the OITS International Conference on Information Technology, 2022

2020

Rectilinear Steiner Tree Construction Techniques Using PB-SAT-Based Methodology.

Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee

J. Circuits Syst. Comput., 2020

2019

Architecture-aware routability-driven placer for large-scale mixed-size designs.

Prasun Datta, Shyamapada Mukherjee

IET Circuits Devices Syst., 2019

Gait Recognition using Segmented Motion Flow Energy Image.

Shyamapada Mukherjee, Kunal Chaudhary, Priya Jain, Bishal Paul

Proceedings of the 10th International Conference on Computing, 2019

Spoken Language Recognition Using CNN.

Shyamapada Mukherjee, Neeraj Shivam, Astha Gangwal, Lokesh Khaitan, Amlan Jyoti Das

Proceedings of the 2019 International Conference on Information Technology (ICIT), 2019

2018

An Alternate Algorithmic Approach to FPGA Placement.

Shyamapada Mukherjee, A. Nainwal, C. C. Das, Sharbani Purkayastha

Proceedings of the 9th International Conference on Computing, 2018

IPplacer: An Efficient 0-1 Integer Programming Based Placement for VLSI Circuits.

Prasun Datta, Shyamapada Mukherjee

Proceedings of the 9th International Conference on Computing, 2018

2017

Via-Aware Dogleg Routing Using Boolean Satisfiability.

Shyamapada Mukherjee, Suchismita Roy

J. Circuits Syst. Comput., 2017

Lookahead legalization based global placement for heterogeneous FPGAs.

Sharbani Purkayastha, Shyamapada Mukherjee

Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

K-nearest neighbour (KNN) approach using SAT based technique for rectilinear steiner tree construction.

Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee

Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

2016

Nearly-2-SAT Solutions for Segmented-Channel Routing.

Shyamapada Mukherjee, Suchismita Roy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2015

SAT based solutions for detailed routing of island style FPGA architectures.

Shyamapada Mukherjee, Suchismita Roy

Microelectron. J., 2015

Multi terminal net routing for island style FPGAs using nearly-2-SAT computation.

Shyamapada Mukherjee, Suchismita Roy

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2013

Congestion Balancing Global Router.

Shyamapada Mukherjee, Jibesh Patra, Suchismita Roy

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013