Siddhartha Raman Sundara Raman

According to our database, Siddhartha Raman Sundara Raman authored at least 13 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Emerging memory technologies at room/cryogenic temperature.

Siddhartha Raman Sundara Raman

CoRR, May, 2026

A complete discussion on fully reconfigurable, digital, scalable, graph and sparsity-aware near-memory accelerator for graph neural networks.

Siddhartha Raman Sundara Raman, Lizy Kurian John, Jaydeep P. Kulkarni

CoRR, May, 2026

A comprehensive study on ILP acceleration accounting for sparsity, area, energy, data movement using near-memory architecture.

Siddhartha Raman Sundara Raman, Lizy K. John, Jaydeep P. Kulkarni

CoRR, May, 2026

A detailed algorithmic study on a reuse-aware, near memory, all-digital Ising machine.

Siddhartha Raman Sundara Raman, Lizy K. John, Jaydeep P. Kulkarni

CoRR, May, 2026

A comparative study on power delivery aspects of compute-in/near-memory approaches using DRAM.

Siddhartha Raman Sundara Raman, Siyuan Ma, Lizy Kurian John

CoRR, April, 2026

ABI: A tightly integrated, unified, sparsity-aware, reconfigurable, compute near-register file/cache GPU architecture with light-weight softmax for deep learning, linear algebra, and Ising compute.

Siddhartha Raman Sundara Raman, Jaydeep P. Kulkarni

CoRR, February, 2026

2025

Unconventional Computing Using Ising Accelerators.

Jaydeep P. Kulkarni, Siddhartha Raman Sundara Raman, Shanshan Xie, Chieh-Pu Lo

Computer, June, 2025

SPARK: Sparsity Aware, Low Area, Energy-Efficient, Near-memory Architecture for Accelerating Linear Programming Problems.

Siddhartha Raman Sundara Raman, Lizy Kurian John, Jaydeep P. Kulkarni

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

2024

NEM-GNN: DAC/ADC-less, Scalable, Reconfigurable, Graph and Sparsity-Aware Near-Memory Accelerator for Graph Neural Networks.

Siddhartha Raman Sundara Raman, Lizy Kurian John, Jaydeep P. Kulkarni

ACM Trans. Archit. Code Optim., June, 2024

SACHI: A Stationarity-Aware, All-Digital, Near-Memory, Ising Architecture.

Siddhartha Raman Sundara Raman, Lizy K. John, Jaydeep P. Kulkarni

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2022

Ising-CIM: A Reconfigurable and Scalable Compute Within Memory Analog Ising Accelerator for Solving Combinatorial Optimization Problems.

Shanshan Xie, Siddhartha Raman Sundara Raman, Can Ni, Meizhi Wang, Mengtian Yang, Jaydeep P. Kulkarni

IEEE J. Solid State Circuits, 2022

Enabling In-Memory Computations in Non-Volatile SRAM Designs.

Siddhartha Raman Sundara Raman, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

2021

Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors.

Siddhartha Raman Sundara Raman, Shanshan Xie, Jaydeep P. Kulkarni

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021