S. S. Teja Nibhanupudi
Orcid: 0000-0001-6733-1910
According to our database1,
S. S. Teja Nibhanupudi
authored at least 8 papers
between 2019 and 2023.
Collaborative distances:
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Bibliography
2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Experimental demonstration of sub-nanosecond switching in 2D hexagonal Boron Nitride resistive memory devices.
Proceedings of the Device Research Conference, 2022
Statistical Analysis of 2T1R Gain-Cell RRAM Bitcell for Area Efficient, High-Performance, and Reliable Multi-level Cell Operation.
Proceedings of the Device Research Conference, 2022
2021
COMPAC: Compressed Time-Domain, Pooling-Aware Convolution CNN Engine With Reduced Data Movement for Energy-Efficient AI Computing.
IEEE J. Solid State Circuits, 2021
2020
A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing.
IEEE J. Solid State Circuits, 2020
2019
All-Digital Time-Domain CNN Engine Using Bidirectional Memory Delay Lines for Energy-Efficient Edge Computing.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Neural Network Assisted Compact Model for Accurate Characterization of Cycle-to-cycle Variations in 2-D $h$-BN based RRAM devices.
Proceedings of the Device Research Conference, 2019