S. S. Teja Nibhanupudi

According to our database, S. S. Teja Nibhanupudi authored at least 10 papers between 2019 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Metal Stack Exploration for Front- Versus Back- Side Clock and Signal Allocation for Advanced CMOS PPA Improvements.

Nishant Gupta, Sirish Oruganti, S. S. Teja Nibhanupudi, Anup Ashok Kedilaya, Xiuhao Zhang, Jaydeep P. Kulkarni

IEEE Trans. Very Large Scale Integr. Syst., June, 2026

2025

Photonic Side-Channel Analyzer: Enabling Security-Aware Physical Design Methodology.

Meizhi Wang, Yi-Ru Chen, S. S. Teja Nibhanupudi, Elham Amini, Antonio Saavedra, Yinan Wang, Daniel Wasserman, Jean-Pierre Seifert, Jaydeep P. Kulkarni

Proceedings of the 2025 International Symposium on Physical Design, 2025

2023

Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges.

S. S. Teja Nibhanupudi, Sirish Oruganti, Rahul Mathur, Nishant Gupta, Meizhi Wang, Jaydeep P. Kulkarni

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Enabling In-Memory Computations in Non-Volatile SRAM Designs.

Siddhartha Raman Sundara Raman, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Experimental demonstration of sub-nanosecond switching in 2D hexagonal Boron Nitride resistive memory devices.

S. S. Teja Nibhanupudi, Dmitry Veksler, Anupam Roy, Matthew Coupin, Kevin C. Matthews, Jamie Warner, Gennadi Bersuker, Jaydeep P. Kulkarni, Sanjay Kumar Banerjee

Proceedings of the Device Research Conference, 2022

Statistical Analysis of 2T1R Gain-Cell RRAM Bitcell for Area Efficient, High-Performance, and Reliable Multi-level Cell Operation.

Rishab Mehra, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni

Proceedings of the Device Research Conference, 2022

2021

COMPAC: Compressed Time-Domain, Pooling-Aware Convolution CNN Engine With Reduced Data Movement for Energy-Efficient AI Computing.

Aseem Sayal, Shirin Fathima, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni

IEEE J. Solid State Circuits, 2021

2020

A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing.

Aseem Sayal, S. S. Teja Nibhanupudi, Shirin Fathima, Jaydeep P. Kulkarni

IEEE J. Solid State Circuits, 2020

2019

All-Digital Time-Domain CNN Engine Using Bidirectional Memory Delay Lines for Energy-Efficient Edge Computing.

Aseem Sayal, Shirin Fathima, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Neural Network Assisted Compact Model for Accurate Characterization of Cycle-to-cycle Variations in 2-D $h$-BN based RRAM devices.

Jacob N. Rohan, Pingping Zhuang, S. S. Teja Nibhanupudi, Sanjay Kumar Banerjee, Jaydeep P. Kulkarni

Proceedings of the Device Research Conference, 2019