Jaydeep P. Kulkarni

Orcid: 0000-0002-0258-6776

According to our database1, Jaydeep P. Kulkarni authored at least 88 papers between 2004 and 2024.

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Bibliography

2024
NEM-GNN: DAC/ADC-less, Scalable, Reconfigurable, Graph and Sparsity-Aware Near-Memory Accelerator for Graph Neural Networks.
ACM Trans. Archit. Code Optim., June, 2024

eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters.
IEEE J. Solid State Circuits, June, 2024

30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

SACHI: A Stationarity-Aware, All-Digital, Near-Memory, Ising Architecture.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

Randomization Approaches for Secure SAR ADC Design Resilient Against Power Side-Channel Attacks.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming Problems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration.
ACM Trans. Reconfigurable Technol. Syst., September, 2023

An In-Memory-Computing Charge-Domain Ternary CNN Classifier.
IEEE J. Solid State Circuits, May, 2023

A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference.
IEEE J. Solid State Circuits, 2023

An Estimator for the Sensitivity to Perturbations of Deep Neural Networks.
CoRR, 2023

Snap-SAT: A One-Shot Energy-Performance-Aware All-Digital Compute-in-Memory Solver for Large-Scale Hard Boolean Satisfiability Problems.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 118 GOPS/mm<sup>2</sup>3D eDRAM TensorCore Architecture for Large-scale Matrix Multiplication.
Proceedings of the 30th IEEE International Conference on High Performance Computing, 2023

CIMGN: An Energy-efficient All-digital Compute-in-memory Graph Neural Network Processor.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

Compute-MLROM: Compute-in-Multi Level Read Only Memory for Energy Efficient Edge AI Inference Engines.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

A GNN Computing-in-Memory Macro and Accelerator with Analog-Digital Hybrid Transformation and CAMenabled Search-reduce.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
Ising-CIM: A Reconfigurable and Scalable Compute Within Memory Analog Ising Accelerator for Solving Combinatorial Optimization Problems.
IEEE J. Solid State Circuits, 2022

Enabling In-Memory Computations in Non-Volatile SRAM Designs.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Guest Editorial Revolution of AI and Machine Learning With Processing-in-Memory (PIM): From Systems, Architectures, to Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

CoMeFa: Compute-in-Memory Blocks for FPGAs.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

Experimental demonstration of sub-nanosecond switching in 2D hexagonal Boron Nitride resistive memory devices.
Proceedings of the Device Research Conference, 2022

Statistical Analysis of 2T1R Gain-Cell RRAM Bitcell for Area Efficient, High-Performance, and Reliable Multi-level Cell Operation.
Proceedings of the Device Research Conference, 2022

Buried-Channel Ferroelectric FET as Energy Efficient and Reliable 1T-NVM.
Proceedings of the Device Research Conference, 2022

Cryo-TRAM: Gated Thyristor based Capacitor-less DRAM for Cryogenic Computing.
Proceedings of the Device Research Conference, 2022

Aging Effects On Clock Gated Memory Phase Paths.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021
COMPAC: Compressed Time-Domain, Pooling-Aware Convolution CNN Engine With Reduced Data Movement for Energy-Efficient AI Computing.
IEEE J. Solid State Circuits, 2021

16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A Systematic Evaluation of EM and Power Side-Channel Analysis Attacks on AES Implementations.
Proceedings of the IEEE International Conference on Intelligence and Security Informatics, 2021

Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Field-Emission Enhanced Contacts for Disordered Semiconductor based Thin-Film Transistors.
Proceedings of the Device Research Conference, 2021

Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

3D-Split SRAM: Enabling Generational Gains in Advanced CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

Realizing Direct Convolution in Memory with Systolic-RAM.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

Trends in Analog and Digital Intensive Compute-in-SRAM Designs.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
M2A2: Microscale Modular Assembled ASICs for High-Mix, Low-Volume, Heterogeneously Integrated Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Chip Design 2020.
IEEE Micro, 2020

A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing.
IEEE J. Solid State Circuits, 2020

Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology.
CoRR, 2020

Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
IEEE J. Solid State Circuits, 2019

All-Digital Time-Domain CNN Engine Using Bidirectional Memory Delay Lines for Energy-Efficient Edge Computing.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Neural Network Assisted Compact Model for Accurate Characterization of Cycle-to-cycle Variations in 2-D $h$-BN based RRAM devices.
Proceedings of the Device Research Conference, 2019

2018
VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing.
ACM J. Emerg. Technol. Comput. Syst., 2018

Report on the 2018 IEEE/ACM International Symposium on Low Power Electronics and Design.
IEEE Des. Test, 2018

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Soft-FET: phase transition material assisted soft switching field effect transistor for supply voltage droop mitigation.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Editorial.
IEEE Trans. Very Large Scale Integr. Syst., 2017

5.6 Mb/mm<sup>2</sup> 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology.
IEEE J. Solid State Circuits, 2017

Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating.
IEEE J. Solid State Circuits, 2017

Message from the program co-chairs.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2016
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging.
IEEE J. Solid State Circuits, 2016

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator.
IEEE J. Solid State Circuits, 2016

17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A novel slope detection technique for robust STTRAM sensing.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2014

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
Improving multi-core performance using mixed-cell cache architecture.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Design for test and reliability in ultimate CMOS.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

2010
Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Resilient design in scaled CMOS for energy efficiency.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Device/circuit interactions at 22nm technology node.
Proceedings of the 46th Design Automation Conference, 2009

REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Thermal analysis of 8-T SRAM for nano-scaled technologies.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Process variation tolerant SRAM array for ultra low voltage applications.
Proceedings of the 45th Design Automation Conference, 2008

A high sensitivity process variation sensor utilizing sub-threshold operation.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM.
IEEE J. Solid State Circuits, 2007

A High Performance, Scalable Multiplexed Keeper Technique.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

2004
A Fast LSF Search Algorithm Based on Interframe Correlation in G.723.1.
EURASIP J. Adv. Signal Process., 2004


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