Simon Rokicki

Orcid: 0000-0002-0195-096X

According to our database1, Simon Rokicki authored at least 14 papers between 2017 and 2024.

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Bibliography

2024
A Unified Memory Dependency Framework for Speculative High-Level Synthesis.
Proceedings of the 33rd ACM SIGPLAN International Conference on Compiler Construction, 2024

2022
SpecHLS: Speculative Accelerator Design Using High-Level Synthesis.
IEEE Micro, 2022

Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis.
Proceedings of the International Conference on Field-Programmable Technology, 2022

RT-DFI: Optimizing Data-Flow Integrity for Real-Time Systems.
Proceedings of the 34th Euromicro Conference on Real-Time Systems, 2022

2020
Toward Speculative Loop Pipelining for High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Attack Detection Through Monitoring of Timing Deviations in Embedded Real-Time Systems.
Proceedings of the 32nd Euromicro Conference on Real-Time Systems, 2020

GhostBusters: Mitigating Spectre Attacks on a DBT-Based Processor.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications.
Proceedings of the International Conference on Computer-Aided Design, 2019

Aggressive Memory Speculation in HW/SW Co-Designed Machines.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Accélération matérielle pour la traduction dynamique de programmes binaires. (Hardware Accelerated Dynamic Binary Translation).
PhD thesis, 2018

Hybrid Obfuscation to Protect Against Disclosure Attacks on Embedded Microprocessors.
IEEE Trans. Computers, 2018

Supporting runtime reconfigurable VLIWs cores through dynamic binary translation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Hardware-accelerated dynamic binary translation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017


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