Russell Tessier

According to our database1, Russell Tessier authored at least 116 papers between 1993 and 2019.

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Bibliography

2019
Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration.
IEEE Trans. VLSI Syst., 2019

Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays.
TRETS, 2019

Introduction to the Special Section on Security in FPGA-accelerated Cloud and Datacenters.
TRETS, 2019

Closed-Loop Proportion-Derivative Control of Suppressing Seizures in a Neural Mass Model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Characterizing Power Distribution Attacks in Multi-User FPGA Environments.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Characterization of Long Wire Data Leakage in Deep Submicron FPGAs.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
On the Difficulty of FSM-based Hardware Obfuscation.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

Hybrid Obfuscation to Protect Against Disclosure Attacks on Embedded Microprocessors.
IEEE Trans. Computers, 2018

A Hardware Monitor to Protect Linux System Calls.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Lynq: A Lightweight Software Layer for Rapid SoC FPGA Prototyping.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

FPGA Side Channel Attacks without Physical Access.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

A Bandwidth-Optimized Routing Algorithm for Hybrid FPGA Networks-on-Chip.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm.
ACM Trans. Embedded Comput. Syst., 2017

HAL- The Missing Piece of the Puzzle for Hardware Reverse Engineering, Trojan Detection and Insertion.
IACR Cryptology ePrint Archive, 2017

Scalable Network Function Virtualization for Heterogeneous Middleboxes.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Energy Efficient Loop Unrolling for Low-Cost FPGAs.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Hardware support for embedded operating system security.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
Dynamic Hardware Monitors for Network Processor Protection.
IEEE Trans. Computers, 2016

Soft GPGPUs for Embedded FPGAs: An Architectural Evaluation.
CoRR, 2016

Hybrid hard NoCs for efficient FPGA communication.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Effects of I/O routing through column interfaces in embedded FPGA fabrics.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
Securing Network Processors with High-Performance Hardware Monitors.
IEEE Trans. Dependable Sec. Comput., 2015

Reconfigurable Computing Architectures.
Proceedings of the IEEE, 2015

Reinforcement Learning for Thermal-aware Many-core Task Allocation.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Adaptive MRAM-based CGRAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Protecting against Cryptographic Trojans in FPGAs.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Hardware-assisted code obfuscation for FPGA soft microprocessors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Multi-task support for security-enabled embedded processors.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
Dynamic On-Chip Thermal Sensor Calibration Using Performance Counters.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

A Broadcast-Enabled Sensing System for Embedded Multi-core Processors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

FPGA architecture support for heterogeneous, relocatable partial bitstreams.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

FPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable Regions.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

System-Level Security for Network Processors with Hardware Monitors.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Configurable memory security in embedded systems.
ACM Trans. Embedded Comput. Syst., 2013

Reconfigurable Data Planes for Scalable Network Virtualization.
IEEE Trans. Computers, 2013

Real-Time Differential Signal Phase Estimation for Space-Based Systems using FPGAs.
IEEE Trans. Aerospace and Electronic Systems, 2013

Accelerating iterative algorithms with asynchronous accumulative updates on FPGAs.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

An open-source SATA core for Virtex-4 FPGAs.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

FlexGrip: A soft GPGPU for FPGAs.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Run-time probabilistic detection of miscalibrated thermal sensors in many-core systems.
Proceedings of the Design, Automation and Test in Europe, 2013

FPGA latency optimization using system-level transformations and DFG restructuring.
Proceedings of the Design, Automation and Test in Europe, 2013

High-performance hardware monitors to protect network processors from data plane attacks.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Scalable hardware monitors to protect network processors from data plane attacks.
Proceedings of the IEEE Conference on Communications and Network Security, 2013

2012
Collaborative calibration of on-chip thermal sensors using performance counters.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Saving energy and improving TCP throughput with rate adaptation in Ethernet.
Proceedings of IEEE International Conference on Communications, 2012

Distributed sensor data processing for many-cores.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
A Dedicated Monitoring Infrastructure for Multicore Processors.
IEEE Trans. VLSI Syst., 2011

Securing the data path of next-generation router systems.
Comput. Commun., 2011

Customizing virtual networks with partial FPGA reconfiguration.
Computer Communication Review, 2011

Evaluation of the Universal Geocast Scheme for VANETs.
Proceedings of the 74th IEEE Vehicular Technology Conference, 2011

Efficient key-dependent message authentication in reconfigurable hardware.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

A Dynamically-Reconfigurable Phased Array Radar Processing System.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

ReClick - A Modular Dataplane Design Framework for FPGA-Based Network Virtualization.
Proceedings of the 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2011

Real-time estimates of differential signal phase for spaceborne systems using FPGAs.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010
Thermal-aware voltage droop compensation for multi-core architectures.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Scalable network virtualization using FPGAs.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

Multicore soft error rate stabilization using adaptive dual modular redundancy.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors.
TACO, 2009

A security approach for off-chip memory in embedded microprocessor systems.
Microprocessors and Microsystems - Embedded Hardware Design, 2009

An Interactive Approach to Timing Accurate PCI-X Simulation.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Design of a Secure Router System for Next-Generation Networks.
Proceedings of the Third International Conference on Network and System Security, 2009

CMOS vs Nano: comrades or rivals?
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Application Specific Customization and Scalability of Soft Multiprocessors.
Proceedings of the FCCM 2009, 2009

A monitor interconnect and support subsystem for multicore processors.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Memory security management for reconfigurable embedded systems.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

2007
Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

FPGA Architecture: Survey and Challenges.
Foundations and Trends in Electronic Design Automation, 2007

Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

Tetris: a new register pressure control technique for VLIW processors.
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

Power-aware FPGA logic synthesis using binary decision diagrams.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Establishing Chain of Trust in Reconfigurable Hardware.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

High-efficiency protection solution for off-chip memory in embedded systems.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

2006
Design-specific path delay testing in lookup-table-based FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Field-Programmable Gate Arrays in Embedded Systems.
EURASIP J. Emb. Sys., 2006

Power-aware RAM mapping for FPGA embedded memory blocks.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

An adaptive Reed-Solomon errors-and-erasures decoder.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2005
A reconfigurable, power-efficient adaptive Viterbi decoder.
IEEE Trans. VLSI Syst., 2005

An energy-aware active smart card.
IEEE Trans. VLSI Syst., 2005

Salient features of radar nodes of the first generation NetRad System.
Proceedings of the IEEE International Geoscience & Remote Sensing Symposium, 2005

2004
Guest Editorial: Field Programmable Logic.
VLSI Signal Processing, 2004

Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations.
VLSI Signal Processing, 2004

Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits.
IEEE Trans. VLSI Syst., 2004

An architecture and compiler for scalable on-chip communication.
IEEE Trans. VLSI Syst., 2004

A pod-based dual-beam SAR.
IEEE Geosci. Remote Sensing Lett., 2004

A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003
Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores.
Proceedings of the 2003 International Conference on Image Processing, 2003

A hybrid adiabatic content addressable memory for ultra low-power applications.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Adaptive Fault Recovery for Networked Reconfigurable Systems.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Floating Point Unit Generation and Evaluation for FPGAs.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

2002
Incremental compilation for parallel logic verification systems.
IEEE Trans. VLSI Syst., 2002

BDD-based logic synthesis for LUT-based FPGAs.
ACM Trans. Design Autom. Electr. Syst., 2002

Fast placement approaches for FPGAs.
ACM Trans. Design Autom. Electr. Syst., 2002

Static scheduling of multidomain circuits for fast functional verification.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Testing and diagnosis of interconnect faults in cluster-based FPGA architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Trading off Reliability and Power-Consumption in Ultra-low Power Systems.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

The Integration of SystemC and Hardware-Assisted Verification.
Proceedings of the Field-Programmable Logic and Applications, 2002

A dynamically reconfigurable adaptive viterbi decoder.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

2001
Reconfigurable Computing for Digital Signal Processing: A Survey.
VLSI Signal Processing, 2001

BIST-based delay path testing in FPGA architectures.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Static Scheduling of Multi-Domain Memories For Functional Verification.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Dynamically parameterized algorithms and architectures to exploit signal variations for improved performance and reduced power.
Proceedings of the IEEE International Conference on Acoustics, 2001

Static Scheduling of Multiple Asynchronous Domains For Functional Verification.
Proceedings of the 38th Design Automation Conference, 2001

2000
Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Balancing Logic Utilization and Area Efficiency in FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2000

Area-Optimized Technology Mapping for Hybrid FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2000

Tolerating operational faults in cluster-based FPGAs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Interconnect testing in cluster-based FPGA architectures.
Proceedings of the 37th Conference on Design Automation, 2000

aSOC: A Scalable, Single-Chip Communications Architecture.
Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000

1999
Fast place and route approaches for field-programmable gate arrays.
PhD thesis, 1999

Incremental Compilation for Logic Emulation.
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

Frontier: A Fast Placement System for FPGAs.
Proceedings of the VLSI: Systems on a Chip, 1999

1997
Logic emulation with virtual wires.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

1993
The NuMesh: A Modular, Scalable Communications Substrate.
Proceedings of the 7th international conference on Supercomputing, 1993


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