Erven Rohou

According to our database1, Erven Rohou authored at least 52 papers between 1997 and 2020.

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Bibliography

2020
Guided just-in-time specialization.
Sci. Comput. Program., 2020

2019
Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Towards automatic binary runtime loop de-parallelization using on-stack replacement.
Inf. Process. Lett., 2019

The ANTAREX Domain Specific Language for High Performance Computing.
CoRR, 2019


Aggressive Memory Speculation in HW/SW Co-Designed Machines.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Energy-Efficient Memory Mappings based on Partial WCET Analysis and Multi-Retention Time STT-RAM.
Proceedings of the 26th International Conference on Real-Time Networks and Systems, 2018

Compile-Time Silent-Store Elimination for Energy Efficiency: an Analytic Evaluation for Non-Volatile Cache Memory.
Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2018

fittChooser: A Dynamic Feedback Based Fittest Optimization Chooser.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

ANTAREX: A DSL-Based Approach to Adaptively Optimizing and Enforcing Extra-Functional Properties in High Performance Computing.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Supporting runtime reconfigurable VLIWs cores through dynamic binary translation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018


2017
Runtime Vectorization Transformations of Binary Code.
International Journal of Parallel Programming, 2017

The W-SEPT Project: Towards Semantic-Aware WCET Estimation.
Proceedings of the 17th International Workshop on Worst-Case Execution Time Analysis, 2017

The ANTAREX tool flow for monitoring and autotuning energy efficient HPC systems.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Dynamic function specialization.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Implications of Reduced-Precision Computations in HPC: Performance, Energy and Error.
Proceedings of the Parallel Computing is Everywhere, 2017

Hardware-accelerated dynamic binary translation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Compile-time function memoization.
Proceedings of the 26th International Conference on Compiler Construction, 2017

2016
Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Autotuning and adaptivity approach for energy efficient Exascale HPC systems: The ANTAREX approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Intercepting Functions for Memoization: A Case Study Using Transcendental Functions.
TACO, 2015

Dynamic re-vectorization of binary code.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Tracing Flow Information for Tighter WCET Estimation: Application to Vectorization.
Proceedings of the 21st IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2015

Sequential Performance: Raising Awareness of the Gory Details.
Proceedings of the International Conference on Computational Science, 2015

ANTAREX - AutoTuning and Adaptivity appRoach for Energy Efficient eXascale HPC Systems.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

Branch prediction and the performance of interpreters: don't trust folklore.
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2015

Infrastructures and Compilation Strategies for the Performance of Computing Systems.
, 2015

2014
A lightweight incremental analysis and profiling framework for embedded devices.
Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, 2014

Traceability of Flow Information: Reconciling Compiler Optimizations and WCET Estimation.
Proceedings of the 22nd International Conference on Real-Time Networks and Systems, 2014

Arbitrary control-flow embedding into multiple threads for obfuscation: a preliminary complexity and performance analysis.
Proceedings of the Second International Workshop on Security in Cloud Computing, 2014

2013
Vectorization technology to improve interpreter performance.
TACO, 2013

Thread-Based Obfuscation through Control-Flow Mangling.
CoRR, 2013

2012
Tiptop: Hardware Performance Counters for the Masses.
Proceedings of the 41st International Conference on Parallel Processing Workshops, 2012

2011
ACOTES Project: Advanced Compiler Technologies for Embedded Streaming.
International Journal of Parallel Programming, 2011

Predictable Binary Code Cache: A First Step towards Reconciling Predictability and Just-in-Time Compilation.
Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium, 2011

Speculatively vectorized bytecode.
Proceedings of the High Performance Embedded Architectures and Compilers, 2011

Vapor SIMD: Auto-vectorize once, run everywhere.
Proceedings of the CGO 2011, 2011

2010
CLI-based compilation flows for the C language.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Processor virtualization and split compilation for heterogeneous multicore embedded systems.
Proceedings of the 47th Design Automation Conference, 2010

2008
An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

Combining Processor Virtualization and Split Compilation for Heterogeneous Multicore Embedded Systems.
Proceedings of the Emerging Uses and Paradigms for Dynamic Binary Translation, 26.10., 2008

08441 Final Report - Emerging Uses and Paradigms for Dynamic Binary Translation.
Proceedings of the Emerging Uses and Paradigms for Dynamic Binary Translation, 26.10., 2008

2005
Comparing the size of .NET applications with native code.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2002
The Impact of Alias Analysis on VLIW Scheduling.
Proceedings of the High Performance Computing, 4th International Symposium, 2002

2000
Handling Global Constraints in Compiler Strategy.
International Journal of Parallel Programming, 2000

1999
Porting an Ocean Code to MPI Using TSF.
Proceedings of the Languages and Compilers for Parallel Computing, 1999

Code Cloning Tracing: A "Pay per Trace" Approach.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

OCEANS - Optimising Compilers for Embedded Applications.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998

1997


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