Sina Balkir

According to our database1, Sina Balkir authored at least 55 papers between 1994 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Hardware-Assisted Compression.
Proceedings of the Encyclopedia of Big Data Technologies., 2019

A Low-Power, Single-Chip Electronic Skin Interface for Prosthetic Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Low Complexity Radioisotope Identification System using an Integrated Multichannel Analyzer and Embedded Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
A Low-Power Radiation Detection System for Portable, Long-Duration Monitoring.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A 1000 frames/s Vision Chip Using Scalable Pixel-Neighborhood-Level Parallel Processing.
J. Solid-State Circuits, 2017

A low-power 10-bit multichannel analyzer chip for radiation detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Real-time trajectory calculation and prediction using neighborhood-level parallel processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Live demonstration: Programmable vision chip with neighborhood level parallel processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Digital Offset Cancellation for Long Time-Constant Subthreshold OTA-C Integrators.
IEEE Trans. on Circuits and Systems, 2015

A programmable vision chip with pixel-neighborhood level parallel processing.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013
Low-Power Analog Processing for Sensing Applications: Low-Frequency Harmonic Signal Classification.
Sensors, 2013

2012
Analog sensing front-end system for harmonic signal classification.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2010
A 4-muhboxW CMOS Front End for Particle Detection Applications.
IEEE Trans. on Circuits and Systems, 2010

A single chip computational sensor system for gamma isotope identification.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Hardware implementation of the double-tree scan architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A Computational Sensor System for Particle Detection Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

The Design of the Baseband Processor of a Non-coherent UWB Receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

The Design of an Ultra-low Power Buck Regulator Supporting Dynamic Voltage Scaling for Wireless Sensor Networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A CMOS Image Sensor for Multi-Level Focal Plane Image Decomposition.
IEEE Trans. on Circuits and Systems, 2008

A Synthesis Tool for CMOS RF Low-Noise Amplifiers.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Pixel sensor integrated neuromorphic VLSI system for real-time applications.
Neurocomputing, 2008

Synthesis of RF CMOS Low Noise Amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A low-power CMOS front end for particle detection applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A CMOS image sensor with focal plane SPIHT image compression.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Predictive coding on-sensor compression.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
A CMOS Imager With Focal Plane Compression Using Predictive Coding.
J. Solid-State Circuits, 2007

A CMOS Front-End for a Lossy Image Compression Sensor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low-Cost, Tiled Embedded Smart Camera System for Computer Vision Applications.
Proceedings of the 2007 First ACM/IEEE International Conference on Distributed Smart Cameras, 2007

2006
Automatic synthesis of CMOS RF front-ends.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A hand-held neutron detection sensor system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Robust front-end design for ultra wideband systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Effects of charge-based computation non-idealities on CMOS image compression sensors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A CMOS imager with focal plane compression.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Optical sensor integrated CNN for real-time computational applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Bio-inspired compact cell circuit for reaction-diffusion systems.
IEEE Trans. on Circuits and Systems, 2005

Design automation of single-ended LNAs using symbolic analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A CMOS image sensor for focal plane decomposition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An analog-to-digital converter with Golomb-Rice output codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A bio-inspired CNN layer with image processing capabilities.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A compact optimization methodology for single-ended LNA.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Charge-based prediction circuits for focal plane image compression.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Evolution Based Synthesis of Analog Integrated Circuits and Systems.
Proceedings of the 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 2004

2003
An evolutionary approach to automatic synthesis of high-performance analog integrated circuits.
IEEE Trans. Evolutionary Computation, 2003

Nanostructure array of coupled RTDs as cellular neural networks.
I. J. Circuit Theory and Applications, 2003

A CMOS imager with pixel prediction for image compression.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Quantum dot networks with weighted coupling.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Evolution-based design of neural fuzzy networks using self-adapting genetic parameters.
IEEE Trans. Fuzzy Systems, 2002

An evolvable predictor for lossless image compression.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Image processing with quantum dot nanostructures.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Robust chaotic PN sequence generation techniques.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Implementation of a New Orthogonal Shuffled Block Transform for Image Coding Applications.
Real-Time Imaging, 2000

1999
ANNSyS: an Analog Neural Network Synthesis System.
Neural Networks, 1999

1998
Incorporating MOS Transistor Mismatches into Training of Analog Neural Networks.
Proceedings of the International ICSC / IFAC Symposium on Neural Computation (NC 1998), 1998

1997
ANNSyS (an analog neural network synthesis system).
Proceedings of International Conference on Neural Networks (ICNN'97), 1997

1994
Numerical integration using Bezier splines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994


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