Ismet Bayraktaroglu

According to our database1, Ismet Bayraktaroglu authored at least 34 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
ChipNeMo: Domain-Adapted LLMs for Chip Design.
CoRR, 2023

2006
Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations.
IEEE Trans. Computers, 2005

Highly Configurable Programmable Built-In Self Test Architecture for High-Speed Memories.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Microprocessor silicon debug based on failure propagation tracing.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test.
IEEE Trans. Reliab., 2004

Seamless Test of Digital Components in Mixed-Signal Paths.
IEEE Des. Test Comput., 2004

ATPG based functional test for data paths: application to a floating point unit.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

2003
Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs.
IEEE Trans. Computers, 2003

Reducing Average and Peak Test Power Through Scan Chain Modification.
J. Electron. Test., 2003

Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Instruction Based BIST for Board/System Level Test of External Memories and Internconnects.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Test application time and volume compression through seed overlapping.
Proceedings of the 40th Design Automation Conference, 2003

2002
Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST.
IEEE Des. Test Comput., 2002

Test Power Reduction through Minimization of Scan Chain Transitions.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Scan Power Reduction Through Test Data Transition Frequency Analysis.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Dynamic test data transformations for average and peak power reductions.
Proceedings of the 7th European Test Workshop, 2002

Gate Level Fault Diagnosis in Scan-Based BIST.
Proceedings of the 2002 Design, 2002

2001
Concurrent test for digital linear systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Improved Methods for Fault Diagnosis in Scan-Based BIST.
Proceedings of the 2nd Latin American Test Workshop, 2001

Diagnosis for scan-based BIST: reaching deep into the signatures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Test Volume and Application Time Reduction Through Scan Chain Concealment.
Proceedings of the 38th Design Automation Conference, 2001

Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck?
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
Invariance-Based On-Line Test for RTL Controller-Datapath Circuits.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Deterministic partitioning techniques for fault diagnosis in scan-based BIST.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Unifying methodologies for high fault coverage concurrent and off-line test of digital filters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Cost effective digital filter design for concurrent test.
Proceedings of the IEEE International Conference on Acoustics, 2000

Low cost concurrent test implementation for linear digital systems.
Proceedings of the 5th European Test Workshop, 2000

Test Synthesis for Mixed-Signal SOC Paths.
Proceedings of the 2000 Design, 2000

Improved fault diagnosis in scan-based BIST via superposition.
Proceedings of the 37th Conference on Design Automation, 2000

Accumulation-based concurrent fault detection for linear digital state variable systems.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
ANNSyS: an Analog Neural Network Synthesis System.
Neural Networks, 1999

Low-Cost On-Line Test for Digital Filters.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

1998
An Examination of PRPG Selection Approaches for Large, Industrial Designs.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998


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