Günhan Dündar

Catherine Dehollain

Proceedings of the 19th International Conference on Synthesis, 2023

Programmable Switched-Capacitor Filter Design Tool for Biomedical Signal Acquisition.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Synthesis, 2023

Jitter Modeling for High Precision Frequency Measurements in Oscillator Circuits.

[BibT_eX]

[DOI]

Utku Arda Akinci

Muhammed Salih Inneci

Zeynep Duygu Sütgöl

Faik Baskaya

Proceedings of the 19th International Conference on Synthesis, 2023

2022

Simulated annealing assisted NSGA-III-based multi-objective analog IC sizing tool.

[BibT_eX]

[DOI]

Integr., 2022

Design Methodology for an Adjustable-Range CMOS Smart Temperature Sensor.

[BibT_eX]

[DOI]

Uygar Yildiz

Kemal Ozanoglu

Proceedings of the 18th International Conference on Synthesis, 2022

An Efficient Hierarchical Approach for Synthesis of Multi-Stage Wide-Band Amplifiers.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Synthesis, 2022

A Simulation Tool for Space Applications: RadiSPICE.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Synthesis, 2022

PLL Based Synchronous Read-Out for Resonant Biosensors.

[BibT_eX]

[DOI]

Zeynep Duygu Sütgöl

Faik Baskaya

Proceedings of the 30th Signal Processing and Communications Applications Conference, 2022

2021

Deep learning aided efficient yield analysis for multi-objective analog integrated circuit synthesis.

[BibT_eX]

[DOI]

Gamze Islamoglu

Tugberk Ogulcan Çakici

Seyda Nur Güzelhan

Integr., 2021

Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test.

[BibT_eX]

[DOI]

Integr., 2021

ACTreS: Analog Clock Tree Synthesis.

[BibT_eX]

[DOI]

CoRR, 2021

2020

Yield-aware multi-objective optimization of a MEMS accelerometer system using QMC-based methodologies.

[BibT_eX]

[DOI]

Microelectron. J., 2020

Experimental Validation of a Novel RLL Code for Visible Light Communication.

[BibT_eX]

[DOI]

Arda Deniz Yalçinkaya

Proceedings of the 43rd International Conference on Telecommunications and Signal Processing, 2020

A High Performance TIA Design in 40 nm CMOS.

[BibT_eX]

[DOI]

Ali Dogus Güngördü

Mustafa Berke Yelten

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Improving POF Quality in Multi Objective Optimization of Analog ICs via Deep Learning.

[BibT_eX]

[DOI]

Tugberk Ogulcan Çakici

Proceedings of the European Conference on Circuit Theory and Design, 2020

2019

On Chip Reconfigurable CMOS Analog Circuit Design and Automation Against Aging Phenomena: Sense and React.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

Analysis, modeling and design of a CMOS Super-Regenerative Receiver for implanted medical devices under square and sinusoidal quench signals.

[BibT_eX]

[DOI]

Naci Pekcokguler

Catherine Dehollain

Integr., 2019

A comprehensive analysis on differential cross-coupled CMOS LC oscillators via multi-objective optimization.

[BibT_eX]

[DOI]

Integr., 2019

Synchronisation free non-coherent on-off keying demodulation techniques.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2019

Artificial Neural Network Assisted Analog IC Sizing Tool.

[BibT_eX]

[DOI]

Gamze Islamoglu

Tugberk Ogulcan Çakici

Proceedings of the 16th International Conference on Synthesis, 2019

Post-Silicon Validation of Yield-Aware Analog Circuit Synthesis.

[BibT_eX]

[DOI]

Gönenç Berkol

Proceedings of the 16th International Conference on Synthesis, 2019

Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Synthesis, 2019

Distance and Power based Experimental Verification of Channel Model in Visible Light Communication.

[BibT_eX]

[DOI]

Proceedings of the 27th Signal Processing and Communications Applications Conference, 2019

Design and Comparison of Low Power Pulse Combining IR-UWB Transmitters in 180nm CMOS.

[BibT_eX]

[DOI]

Semih Ramazanoglu

Okan Zafer Batur

Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

Hysteretic Buck-Boost Converter for Wearable Applications.

[BibT_eX]

[DOI]

Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

2018

Analog behavioral equivalence boundary computation under the effect of process variations.

[BibT_eX]

[DOI]

Alper Sen

Integr., 2018

A novel equivalent circuit model for split ring resonator with an application of low phase noise reference oscillator.

[BibT_eX]

[DOI]

Integr., 2018

A novel design methodology for the mixed-domain optimization of a MEMS accelerometer.

[BibT_eX]

[DOI]

Integr., 2018

Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017.

[BibT_eX]

[DOI]

Giulia Di Capua

Nuno Horta

Integr., 2018

An Analog/RF Circuit Synthesis and Design Assistant Tool for Analog IP: DATA-IP.

[BibT_eX]

[DOI]

Ezgi Kaya

Proceedings of the 15th International Conference on Synthesis, 2018

Design Space Exploration of CMOS Cross-Coupled LC Oscillators via RF Circuit Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Synthesis, 2018

Design and Modelling of a Super-Regenerative Receiver for Medical Implant Devices.

[BibT_eX]

[DOI]

Naci Pekcokguler

Catherine Dehollain

Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

A Rare Event Based Yield Estimation Methodology for Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017

An Integrated Dual Entropy Core True Random Number Generator.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Introduction to the special issue on PRIME 2016 and SMACD 2016.

[BibT_eX]

[DOI]

Nuno Horta

Andrea Baschirotto

João Goes

Jorge Fernandes

Integr., 2017

A standard cell phase locked loop design, analysis and high-level synthesis tool (CellPLL).

[BibT_eX]

[DOI]

Integr., 2017

Aging signature properties and an efficient signature determination tool for online monitoring.

[BibT_eX]

[DOI]

Integr., 2017

A 0.65-1.35 GHz synthesizable all-digital phase locked loop with quantization noise suppressing time-to-digital converter.

[BibT_eX]

[DOI]

Turkish J. Electr. Eng. Comput. Sci., 2017

Low power 3rd order feedforward sigma delta ADC design.

[BibT_eX]

[DOI]

Feyyaz Melih Akçakaya

Turkish J. Electr. Eng. Comput. Sci., 2017

Optimization of a MEMS accelerometer using a multiobjective evolutionary algorithm.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Synthesis, 2017

LNA-ESD-PCB codesign for robust operation of IR-UWB non-coherent receiver.

[BibT_eX]

[DOI]

Okan Zafer Batur

Mutlu Koca

Proceedings of the 14th International Conference on Synthesis, 2017

Compact model based design space exploration for CMOS hall effect sensors.

[BibT_eX]

[DOI]

Ibrahim Kagan Aksoyak

Kaan Balaban

Hamdi Torun

Proceedings of the 14th International Conference on Synthesis, 2017

Review: Analog design methodologies for reliability in nanoscale CMOS circuits.

[BibT_eX]

[DOI]

Mustafa Berke Yelten

Proceedings of the 14th International Conference on Synthesis, 2017

Inversion coefficient optimization assisted analog circuit sizing tool.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Synthesis, 2017

Noise Analysis in Switched Capacitor Amplifier Based Sensors.

[BibT_eX]

[DOI]

Mohammad Ali Vosoughi

Hamdi Torun

Proceedings of the New Generation of CAS, 2017

2016

An analog circuit synthesis tool based on efficient and reliable yield estimation.

[BibT_eX]

[DOI]

Microelectron. J., 2016

An analog behavioral equivalence boundary search methodology for simulink models and circuit level designs utilizing evolutionary computation.

[BibT_eX]

[DOI]

Gönenç Berkol

Alper Sen

Integr., 2016

Comparison of QMC-based yield-aware pareto front techniques for multi-objective robust analog synthesis.

[BibT_eX]

[DOI]

Integr., 2016

Effects of aging and compensation mechanisms in ordering based RO-PUFs.

[BibT_eX]

[DOI]

Integr., 2016

Introduction to the special issue on SMACD 2015.

[BibT_eX]

[DOI]

Nuno Horta

Integr., 2016

A lifetime-aware analog circuit sizing tool.

[BibT_eX]

[DOI]

Integr., 2016

MATLAB & VHDL-AMS co-simulation environment for IR-UWB transceiver design.

[BibT_eX]

[DOI]

Okan Zafer Batur

Mutlu Koca

Proceedings of the 13th International Conference on Synthesis, 2016

Efficient signature selection tool for sense & react systems.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Synthesis, 2016

Semi-empirical aging model development via accelerated aging test.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Synthesis, 2016

Noise analysis of current mode differential integrators.

[BibT_eX]

[DOI]

Hikmet Celiker

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A hierarchical design automation concept for analog circuits.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A mixed domain sizing approach for RF circuit synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015

An Optically Powered CMOS Tracking System for 3 T Magnetic Resonance Environment.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2015

On the convex formulation of area for slicing floorplans.

[BibT_eX]

[DOI]

Integr., 2015

Enhanced challenge-response set and secure usage scenarios for ordering-based ring oscillator-physical unclonable functions.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2015

An efficient grouping method and error probability analysis for RO-PUFs.

[BibT_eX]

[DOI]

Comput. Secur., 2015

Improved standard cell synthesizable Digitally Controlled Oscillator.

[BibT_eX]

[DOI]

Proceedings of the 2015 23nd Signal Processing and Communications Applications Conference (SIU), 2015

A two-step layout-in-the-loop design automation tool.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

A synthesizable Time to Digital Converter (TDC) with MIMO spatial oversampling method.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

A novel yield aware multi-objective analog circuit optimization tool.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A high resolution and low jitter linear delay line for IR-UWB template pulse synchronization.

[BibT_eX]

[DOI]

Proceedings of the European Conference on Circuit Theory and Design, 2015

A hybrid Quasi Monte Carlo method for yield aware analog circuit sizing tool.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Modeling CMOS Ring Oscillator Performance as a Randomness Source.

[BibT_eX]

[DOI]

Ülkühan Güler

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Fast and Efficient Circuit Topologies forFinding the Maximum of n k-Bit Numbers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Reliability assessment of CMOS differential cross-coupled LC oscillators and a novel on chip self-healing approach against aging phenomena.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2014

A novel design method for discrete time chaos based true random number generators.

[BibT_eX]

[DOI]

Integr., 2014

Reliability enhancement using in-field monitoring and recovery for RF circuits.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Model based hierarchical optimization strategies for analog design automation.

[BibT_eX]

[DOI]

Simge Ay

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Analysis of Ring Oscillator structures to develop a design methodology for RO-PUF circuits.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Random number generation using field programmable analog array implementation of logistic map.

[BibT_eX]

[DOI]

Proceedings of the 21st Signal Processing and Communications Applications Conference, 2013

Field programmable analog array implementation of logistic map.

[BibT_eX]

[DOI]

Proceedings of the 21st Signal Processing and Communications Applications Conference, 2013

Synthesis of clock trees for Sampled-Data Analog IC blocks.

[BibT_eX]

[DOI]

Proceedings of the East-West Design & Test Symposium, 2013

A chaos based integrated jitter booster circuit for true random number generators.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Area optimization on fixed analog floorplans using convex area functions.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

A Fast Circuit Topology for Finding the Maximum of N k-bit Numbers.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Symposium on Computer Arithmetic, 2013

2012

FISH: Fast Instruction SyntHesis for Custom Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

An Ultra Low-Power Dual-Band IR-UWB Transmitter in 130-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

An Optically Powered CMOS Receiver System for Intravascular Magnetic Resonance Applications.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A feasibility study of a 1D chaotic map for True Random Number Generation.

[BibT_eX]

[DOI]

Proceedings of the 20th Signal Processing and Communications Applications Conference, 2012

Determining the quality metrics for PUFs and performance evaluation of Two RO-PUFs.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011

Simulation-based analog and RF circuit synthesis using a modified evolutionary strategies algorithm.

[BibT_eX]

[DOI]

Özsun S. Sönmez

Integr., 2011

MOS only simulated grounded negative resistors.

[BibT_eX]

[DOI]

Abdullah Sunca

Oguzhan Cicekoglu

Proceedings of the 34th International Conference on Telecommunications and Signal Processing (TSP 2011), 2011

A hardware efficient chaotic ring oscillator based true random number generator.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

LDS - A description script for layout templates.

[BibT_eX]

[DOI]

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

A template router.

[BibT_eX]

[DOI]

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

Maximizing randomness in ring oscillators for security applications.

[BibT_eX]

[DOI]

Ülkühan Güler

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

A digital IC Random Number Generator with logic gates only.

[BibT_eX]

[DOI]

Ülkühan Güler

Salih Ergün

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

Analog Layout Generator for CMOS Circuits.

[BibT_eX]

[DOI]

Ender Yilmaz

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A Sigma-Delta ADC design automation tool with embedded performance estimator.

[BibT_eX]

[DOI]

Selçuk Talay

Engin Deniz Diktas

Integr., 2009

2008

Computing Gradient Vector and Jacobian Matrix in Arbitrarily Connected Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., 2008

Optimization Using a Modified Second-Order Approach With Evolutionary Enhancement.

[BibT_eX]

[DOI]

Joel D. Hewlett

Bogdan M. Wilamowski

IEEE Trans. Ind. Electron., 2008

An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters.

[BibT_eX]

[DOI]

Mustafa Aktan

Arda Yurdakul

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

CHIPS: Custom Hardware Instruction Processor Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Fast custom instruction identification by convex subgraph enumeration.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007

A coefficient optimization and architecture selection tool for SD modulators considering component non-idealities.

[BibT_eX]

[DOI]

Ömer Yetik

Selçuk Talay

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

New layout generator for analog CMOS circuits.

[BibT_eX]

[DOI]

Ender Yilmaz

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Current-mode circuits for sigma-delta converters.

[BibT_eX]

[DOI]

Ufuk Yapar

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Interactive presentation: A coefficient optimization and architecture selection tool for SigmaDelta modulators in MATLAB.

[BibT_eX]

[DOI]

Ömer Yetik

Selçuk Talay

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Optimizing instruction-set extensible processors under data bandwidth constraints.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Phase noise in bipolar and CMOS VCO's - an analytical comparison.

[BibT_eX]

[DOI]

Baris Koc

Adil Koukab

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Scaling Input Signal Swings of Overloaded Integrators in Resonator-based Sigma-Delta Modulators.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005

Design of Digital Filters for Low Power Applications Using Integer Quadratic Programming.

[BibT_eX]

[DOI]

Mustafa Aktan

Proceedings of the Integrated Circuit and System Design, 2005

Performance estimator for an analog design automation system using EKV-modeled analog circuits.

[BibT_eX]

[DOI]

Engin Deniz

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

A single chip solution for text-to-speech synthesis.

[BibT_eX]

[DOI]

Ozan Aktan

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

An integer linear programming approach for identifying instruction-set extensions.

[BibT_eX]

[DOI]

Kubilay Atasu

Can C. Özturan

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004

Evolution Based Synthesis of Analog Integrated Circuits and Systems.

[BibT_eX]

[DOI]

Sina Balkir

Güner Alpaydin

Proceedings of the 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 2004

2003

An evolutionary approach to automatic synthesis of high-performance analog integrated circuits.

[BibT_eX]

[DOI]

Güner Alpaydin

Sina Balkir

IEEE Trans. Evol. Comput., 2003

2002

Evolution-based design of neural fuzzy networks using self-adapting genetic parameters.

[BibT_eX]

[DOI]

Güner Alpaydin

Sina Balkir

IEEE Trans. Fuzzy Syst., 2002

A new approach to modeling statistical variations in MOS transistors.

[BibT_eX]

[DOI]

Gülin Tulunay

A. Ataman

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

Hierarchical neuro-fuzzy call admission controller for ATM networks.

[BibT_eX]

[DOI]

A. Chatovich

Sema Oktug

Comput. Commun., 2001

Analytical current model for dual-gate MOSFET.

[BibT_eX]

[DOI]

Koray Karahaliloglu

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Weight Quantization for Multi-layer Perceptrons Using Soft Weight Sharing.

[BibT_eX]

[DOI]

Fatih Köksal

Ethem Alpaydin

Proceedings of the Artificial Neural Networks, 2001

2000

Implementation of a New Orthogonal Shuffled Block Transform for Image Coding Applications.

[BibT_eX]

[DOI]

Real Time Imaging, 2000

VLSI implementation of GRBF (Gaussian radial basis function) networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

Multiplierless Realization of Linear DSP Transforms by Using Common Two-Term Expressions.

[BibT_eX]

[DOI]

Arda Yurdakul

J. VLSI Signal Process., 1999

Statistical methods for the estimation of quantization effects in FIR-based multirate systems.

[BibT_eX]

[DOI]

Arda Yurdakul

IEEE Trans. Signal Process., 1999

ANNSyS: an Analog Neural Network Synthesis System.

[BibT_eX]

[DOI]

Neural Networks, 1999

1998

Comments on "The effects of quantization on multilayer neural networks" [and reply].

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 1998

Authors' Reply.

[BibT_eX]

[DOI]

K. Rose

IEEE Trans. Neural Networks, 1998

Incorporating MOS Transistor Mismatches into Training of Analog Neural Networks.

[BibT_eX]

Proceedings of the International ICSC / IFAC Symposium on Neural Computation (NC 1998), 1998

1996

Effects of Nonlinear Synapses on the Performance of Multilayer Neural Networks.

[BibT_eX]

[DOI]

F.-C. Hsu

K. Rose

Neural Comput., 1996

1995

The effects of quantization on multilayer neural networks.

[BibT_eX]

[DOI]