Sitaran Yadavalli

According to our database1, Sitaran Yadavalli authored at least 2 papers between 1995 and 1999.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

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Bibliography

1999
SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1995
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995


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