Irith Pomeranz

According to our database1, Irith Pomeranz authored at least 623 papers between 1991 and 2020.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 1999, "For contributions to the area of test generation for digital logic circuits.".

Timeline

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Bibliography

2020
Extra Clocking of LFSR Seeds for Improved Path Delay Fault Coverage.
IEEE Trans. VLSI Syst., 2020

Selection of Primary Output Vectors to Observe Under Multicycle Tests.
IEEE Trans. VLSI Syst., 2020

Multicycle Broadside and Skewed-Load Tests for Test Compaction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2020

2019
Padding of Multicycle Broadside and Skewed-Load Tests.
IEEE Trans. VLSI Syst., 2019

Extended Transparent-Scan.
IEEE Trans. VLSI Syst., 2019

Test Scores for Improving the Accuracy of Logic Diagnosis for Multiple Defects.
IEEE Trans. VLSI Syst., 2019

Extracting a Close-to-Minimum Multicycle Functional Broadside Test Set From a Functional Test Sequence.
IEEE Trans. VLSI Syst., 2019

Test Compaction by Test Removal Under Transparent Scan.
IEEE Trans. VLSI Syst., 2019

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design.
ACM Trans. Design Autom. Electr. Syst., 2019

Incomplete Tests for Undetectable Faults to Improve Test Set Quality.
ACM Trans. Design Autom. Electr. Syst., 2019

Boundary-Functional Broadside and Skewed-Load Tests.
ACM Trans. Design Autom. Electr. Syst., 2019

Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Skewed-Load Tests for Transition and Stuck-at Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

LFSR-Based Test Generation for Path Delay Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Diagnostic Test Generation That Addresses Diagnostic Holes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Updating the sets of target faults during test generation for multiple fault models.
IET Computers & Digital Techniques, 2019

Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Test Compaction Under Bounded Transparent-Scan.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation.
Proceedings of the IEEE International Test Conference, 2019

Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults.
Proceedings of the IEEE International Test Conference, 2019

Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

TEA: A Test Generation Algorithm for Designs with Timing Exceptions.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018
Observation Points on State Variables for the Compaction of Multicycle Tests.
IEEE Trans. VLSI Syst., 2018

Selecting Functional Test Sequences for Defect Diagnosis.
IEEE Trans. VLSI Syst., 2018

Dynamically Determined Preferred Values and a Design-for-Testability Approach for Multiplexer Select Inputs under Functional Test Sequences.
ACM Trans. Design Autom. Electr. Syst., 2018

Partially Invariant Patterns for LFSR-Based Generation of Close-to-Functional Broadside Tests.
ACM Trans. Design Autom. Electr. Syst., 2018

Autonomous Multicycle Tests With Low Storage and Test Application Time Overheads.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

An Initialization Process to Support Online Testing Based on Output Comparison for Identical Finite-State Machines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Improving the Diagnosability of Scan Chain Faults Under Transparent-Scan by Observation Points.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Static test compaction procedure for large pools of multicycle functional broadside tests.
IET Computers & Digital Techniques, 2018

On-chip generation of primary input sequences for multicycle functional broadside tests.
IET Computers & Digital Techniques, 2018

On Close-to-Functional Test Sequences.
Proceedings of the IEEE International Test Conference, 2018

Interconnect-aware tests to complement gate-exhaustive tests.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Covering undetected transition fault sites with optimistic unspecified transition faults under multicycle tests.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

Postprocessing Procedure for Reducing the Faulty Switching Activity of a Low-Power Test Set.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

2017
Selecting Replacements for Undetectable Path Delay Faults.
IEEE Trans. VLSI Syst., 2017

Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction.
IEEE Trans. VLSI Syst., 2017

Test Modification for Reduced Volumes of Fail Data.
ACM Trans. Design Autom. Electr. Syst., 2017

Generation of Transparent-Scan Sequences for Diagnosis of Scan Chain Faults.
ACM Trans. Design Autom. Electr. Syst., 2017

Computation of Seeds for LFSR-Based n-Detection Test Generation.
ACM Trans. Design Autom. Electr. Syst., 2017

Close-to-Functional Broadside Tests With a Safety Margin.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Restoration-Based Merging of Functional Test Sequences.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Clock Sequences for Increasing the Fault Coverage of Functional Test Sequences.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Identifying Biases of a Defect Diagnosis Procedure.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

LFSR-Based Generation of Multicycle Tests.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Sequential Test Generation Based on Preferred Primary Input Cubes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

New Techniques to Reduce the Execution Time of Functional Test Programs.
IEEE Trans. Computers, 2017

Metric for the ability of functional capture cycles to ensure functional operation conditions.
IET Computers & Digital Techniques, 2017

Reconstruction of a functional test sequence for increased fault coverage.
IET Computers & Digital Techniques, 2017

Using piecewise-functional broadside tests for functional broadside test compaction.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Fail data reduction for diagnosis of scan chain faults under transparent-scan.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure.
Proceedings of the IEEE International Test Conference, 2017

POSTT: Path-oriented static test compaction for transition faults in scan circuits.
Proceedings of the IEEE International Test Conference, 2017

Selecting target bridging faults for uniform circuit coverage.
Proceedings of the IEEE International Test Conference, 2017

Functional Broadside Test Generation Using a Commercial ATPG Tool.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Static Compaction by Merging of Seeds for LFSR-Based Test Generation.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A bridging fault model for line coverage in the presence of undetected transition faults.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Compaction of a Transparent-Scan Sequence to Reduce the Fail Data Volume for Scan Chain Faults.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

Test Compaction with Dynamic Updating of Faults for Coverage of Undetected Transition Fault Sites.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis.
IEEE Trans. VLSI Syst., 2016

Computing Seeds for LFSR-Based Test Generation From Nontest Cubes.
IEEE Trans. VLSI Syst., 2016

Diagnostic Fail Data Minimization Using an N-Cover Algorithm.
IEEE Trans. VLSI Syst., 2016

Periodic Scan-In States to Reduce the Input Test Data Volume for Partially Functional Broadside Tests.
ACM Trans. Design Autom. Electr. Syst., 2016

N-Detection Test Sets for Circuits with Multiple Independent Scan Chains.
ACM Trans. Design Autom. Electr. Syst., 2016

Design-for-Testability for Functional Broadside Tests under Primary Input Constraints.
ACM Trans. Design Autom. Electr. Syst., 2016

Static Test Compaction for Functional Test Sequences With Restoration of Functional Switching Activity.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Balancing the Numbers of Detected Faults for Improved Test Set Quality.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

LFSR-Based Generation of Partially-Functional Broadside Tests.
IEEE Trans. Computers, 2016

Improving the Accuracy of Defect Diagnosis with Multiple Sets of Candidate Faults.
IEEE Trans. Computers, 2016

Combined input test data volume reduction for mixed broadside and skewed-load test sets.
IET Computers & Digital Techniques, 2016

Improving the accuracy of defect diagnosis by adding and removing tests.
IET Computers & Digital Techniques, 2016

Static test compaction for circuits with multiple independent scan chains.
IET Computers & Digital Techniques, 2016

A convergent procedure for partially-reachable states.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

A Compact Set of Seeds for LFSR-Based Test Generation from a Fully-Specified Compact Test Set.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

On the Switching Activity in Faulty Circuits During Test Application.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Test Compaction by Sharing of Functional Test Sequences Among Logic Blocks.
IEEE Trans. VLSI Syst., 2015

Modeling a Set of Functional Test Sequences as a Single Sequence for Test Compaction.
IEEE Trans. VLSI Syst., 2015

Static Test Compaction for Low-Power Test Sets by Increasing the Switching Activity.
IEEE Trans. VLSI Syst., 2015

Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set.
IEEE Trans. VLSI Syst., 2015

Enhanced Test Compaction for Multicycle Broadside Tests by Using State Complementation.
ACM Trans. Design Autom. Electr. Syst., 2015

FOLD: Extreme Static Test Compaction by Folding of Functional Test Sequences.
ACM Trans. Design Autom. Electr. Syst., 2015

A Generalized Definition of Unnecessary Test Vectors in Functional Test Sequences.
ACM Trans. Design Autom. Electr. Syst., 2015

Computation of Seeds for LFSR-Based Diagnostic Test Generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

A Multicycle Test Set Based on a Two-Cycle Test Set With Constant Primary Input Vectors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Test Vector Omission for Fault Coverage Improvement of Functional Test Sequences.
IEEE Trans. Computers, 2015

Two-Dimensional Static Test Compaction for Functional Test Sequences.
IEEE Trans. Computers, 2015

Piecewise-Functional Broadside Tests Based on Reachable States.
IEEE Trans. Computers, 2015

Use of input necessary assignments for test generation based on merging of test cubes.
IET Computers & Digital Techniques, 2015

A definition of the number of detections for faults with single tests in a compact scan-based test set.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Test compaction by test cube merging for four-way bridging faults.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Test vector omission with minimal sets of simulated faults.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Improving the accuracy of defect diagnosis by considering reduced diagnostic information.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Reducing the Storage Requirements of a Set of Functional Test Sequences by Using a Background Sequence.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

FaultHound: value-locality-based soft-fault tolerance.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

On test program compaction.
Proceedings of the 20th IEEE European Test Symposium, 2015

Piecewise-functional broadside tests based on intersections of reachable states.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Generation of close-to-functional broadside tests with equal primary input vectors.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Low-Power Diagnostic Test Sets for Transition Faults Based on Functional Broadside Tests.
IEEE Trans. VLSI Syst., 2014

Low-Power Test Generation by Merging of Functional Broadside Test Cubes.
IEEE Trans. VLSI Syst., 2014

Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks.
IEEE Trans. VLSI Syst., 2014

Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences.
IEEE Trans. VLSI Syst., 2014

Design-for-testability for multi-cycle broadside tests by holding of state variables.
ACM Trans. Design Autom. Electr. Syst., 2014

Low-power skewed-load tests based on functional broadside tests.
ACM Trans. Design Autom. Electr. Syst., 2014

Improving the Accuracy of Defect Diagnosis by Considering Fewer Tests.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Functional Broadside Tests for Multistep Defect Diagnosis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Simultaneous Generation of Functional and Low-Power Non-Functional Broadside Tests.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Selection of Functional Test Sequences With Overlaps.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Unknown Output Values of Faulty Circuits and Output Response Compaction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Sharing Logic for Built-In Generationof Functional Broadside Tests.
IEEE Trans. Computers, 2014

Multi-cycle broadside tests with runs of constant primary input vectors.
IET Computers & Digital Techniques, 2014

Reducing the input test data volume under transparent scan.
IET Computers & Digital Techniques, 2014

On the use of multi-cycle tests for storage of two-cycle broadside tests.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Fault simulation with test switching for static test compaction.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Innovative practices session 10C: Advances in DFT and compression.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

OBO: An Output-by-Output Scoring Algorithm for Fault Diagnosis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

FDPIC: Generation of Functional Test Sequences Based on Fault-Dependent Primary Input Cubes.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Built-in generation of functional broadside tests considering primary input constraints.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A distance-based test cube merging procedure for compatible and incompatible test cubes.
Proceedings of the 19th IEEE European Test Symposium, 2014

Substituting transition faults with path delay faults as a basic delay fault model.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Test and non-test cubes for diagnostic test generation based on merging of test cubes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Functional Broadside Templates for Low-Power Test Generation.
IEEE Trans. VLSI Syst., 2013

On Test Compaction of Broadside and Skewed-Load Test Cubes.
IEEE Trans. VLSI Syst., 2013

Transition Fault Simulation Considering Broadside Tests as Partially-Functional Broadside Tests.
IEEE Trans. VLSI Syst., 2013

Reduced Power Transition Fault Test Sets for Circuits With Independent Scan Chain Modes.
IEEE Trans. VLSI Syst., 2013

Broadside and Skewed-Load Tests Under Primary Input Constraints.
IEEE Trans. VLSI Syst., 2013

Computing Two-Pattern Test Cubes for Transition Path Delay Faults.
IEEE Trans. VLSI Syst., 2013

Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure.
IEEE Trans. VLSI Syst., 2013

Built-in generation of multicycle functional broadside tests with observation points.
ACM Trans. Design Autom. Electr. Syst., 2013

Non-Test Cubes for Test Generation Targeting Hard-to-Detect Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Functional Broadside Tests With Incompletely Specified Scan-In States.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Generation of Functional Broadside Tests for Logic Blocks With Constrained Primary Input Sequences.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Signal-Transition Patterns of Functional Broadside Tests.
IEEE Trans. Computers, 2013

An Adjacent Switching Activity Metric under Functional Broadside Tests.
IEEE Trans. Computers, 2013

Diagnostic Test Sets with Increased Switching Activity for Transition Faults.
J. Low Power Electronics, 2013

Low-power test sets under test-related primary input constraints.
IJCCBS, 2013

On multi-cycle test cubes.
IET Computers & Digital Techniques, 2013

Static test compaction for mixed broadside and skewed-load transition fault test sets.
IET Computers & Digital Techniques, 2013

Path selection based on static timing analysis considering input necessary assignments.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Generation of compact multi-cycle diagnostic test sets.
Proceedings of the 18th IEEE European Test Symposium, 2013

Classes of difficult-to-diagnose transition fault clusters.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Resolution of Diagnosis Based on Transition Faults.
IEEE Trans. VLSI Syst., 2012

Non-Uniform Coverage by n -Detection Test Sets.
IEEE Trans. VLSI Syst., 2012

Generation of Mixed Test Sets for Transition Faults.
IEEE Trans. VLSI Syst., 2012

Multi-Pattern $n$-Detection Stuck-At Test Sets for Delay Defect Coverage.
IEEE Trans. VLSI Syst., 2012

Gradual Diagnostic Test Generation and Observation Point Insertion Based on the Structural Distance Between Indistinguished Fault Pairs.
IEEE Trans. VLSI Syst., 2012

A Metric for Identifying Detectable Path Delay Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Multicycle Tests With Constant Primary Input Vectors for Increased Fault Coverage.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Multipattern Scan-Based Test Sets With Small Numbers of Primary Input Sequences.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

On the Switching Activity and Static Test Compaction of Multicycle Scan-Based Tests.
IEEE Trans. Computers, 2012

Fast Identification of Undetectable Transition Faults under Functional Broadside Tests.
IEEE Trans. Computers, 2012

Concatenation of Functional Test Subsequences for Improved Fault Coverage and Reduced Test Length.
IEEE Trans. Computers, 2012

On the Computation of Common Test Data for Broadside and Skewed-Load Tests.
IEEE Trans. Computers, 2012

Reset and partial-reset-based functional broadside tests.
IET Computers & Digital Techniques, 2012

Functional broadside tests for embedded logic blocks.
IET Computers & Digital Techniques, 2012

Undetectable transition faults under broadside tests with constant primary input vectors.
IET Computers & Digital Techniques, 2012

Test vector chains for increased resolution and reduced storage of diagnostic tests.
IET Computers & Digital Techniques, 2012

Static test compaction for transition faults under the hazard-based detection conditions.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

TSV and DFT cost aware circuit partitioning for 3D-SOCs.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Performance aware partitioning for 3D-SOCs.
Proceedings of the International SoC Design Conference, 2012

On the detection of path delay faults by functional broadside tests.
Proceedings of the 17th IEEE European Test Symposium, 2012

Maintaining proximity to functional operation conditions under enhanced-scan tests based on functional broadside tests.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Built-in generation of multi-cycle broadside tests.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Generation and compaction of mixed broadside and skewed-load n-detection test sets for transition faults.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits.
IEEE Trans. VLSI Syst., 2011

Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors.
IEEE Trans. VLSI Syst., 2011

Static Test Data Volume Reduction Using Complementation or Modulo- M Addition.
IEEE Trans. VLSI Syst., 2011

Broadside and Functional Broadside Tests for Partial-Scan Circuits.
IEEE Trans. VLSI Syst., 2011

On Functional Broadside Tests With Functional Propagation Conditions.
IEEE Trans. VLSI Syst., 2011

Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits.
IEEE Trans. VLSI Syst., 2011

Fixed-State Tests for Delay Faults in Scan Designs.
IEEE Trans. VLSI Syst., 2011

Reducing the switching activity of test sequences under transparent-scan.
ACM Trans. Design Autom. Electr. Syst., 2011

Subsets of Primary Input Vectors in Sequential Test Generation for Single Stuck-at Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Scan Shift Power of Functional Broadside Tests.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Generation of Multi-Cycle Broadside Tests.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan.
J. Low Power Electronics, 2011

Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation.
IET Computers & Digital Techniques, 2011

Sizes of test sets for path delay faults using strong and weak non-robust tests.
IET Computers & Digital Techniques, 2011

Two-dimensional partially functional broadside tests.
IET Computers & Digital Techniques, 2011

Primary input cones based on test sequences in synchronous sequential circuits.
IET Computers & Digital Techniques, 2011

On clustering of undetectable transition faults in standard-scan circuits.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Static test compaction for delay fault test sets consisting of broadside and skewed-load tests.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Generation of Mixed Broadside and Skewed-Load Diagnostic Test Sets for Transition Faults.
Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing, 2011

Augmenting Functional Broadside Tests for Transition Fault Coverage with Bounded Switching Activity.
Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing, 2011

On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests.
Proceedings of the 16th European Test Symposium, 2011

Max-Fill: A method to generate high quality delay tests.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Built-in generation of functional broadside tests.
Proceedings of the Design, Automation and Test in Europe, 2011

Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing.
Proceedings of the Design, Automation and Test in Europe, 2011

Diagnosis of transition fault clusters.
Proceedings of the 48th Design Automation Conference, 2011

Fault diagnosis aware ATE assisted test response compaction.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Selection of a Fault Model for Fault Diagnosis Based on Unique Responses.
IEEE Trans. VLSI Syst., 2010

Switching Activity as a Test Compaction Heuristic for Transition Faults.
IEEE Trans. VLSI Syst., 2010

Robust Fault Models Where Undetectable Faults Imply Logic Redundancy.
IEEE Trans. VLSI Syst., 2010

Path Selection for Transition Path Delay Faults.
IEEE Trans. VLSI Syst., 2010

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests.
IEEE Trans. VLSI Syst., 2010

On Undetectable Faults and Fault Diagnosis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

On Test Generation With Test Vector Improvement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

TOV: Sequential Test Generation by Ordering of Test Vectors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis.
IEEE Trans. Computers, 2010

Test Sequences with Reduced and Increased Switching Activity.
J. Low Power Electronics, 2010

Static test compaction for diagnostic test sets of full-scan circuits.
IET Computers & Digital Techniques, 2010

Diagnosis of path delay faults based on low-coverage tests.
IET Computers & Digital Techniques, 2010

On multiple bridging faults.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Forming multi-cycle tests for delay faults by concatenating broadside tests.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Defect diagnosis based on DFM guidelines.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Output-Dependent Diagnostic Test Generation.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Multiple fault activation cycle tests for transistor stuck-open faults.
Proceedings of the 2011 IEEE International Test Conference, 2010

Selecting state variables for improved on-line testability through output response comparison of identical circuits.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Deterministic broadside test generation for transition path delay faults.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Input test data volume reduction based on test vector chains.
Proceedings of the 15th European Test Symposium, 2010

Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

On reset based functional broadside tests.
Proceedings of the Design, Automation and Test in Europe, 2010

Reducing the storage requirements of a test sequence by using a background vector.
Proceedings of the Design, Automation and Test in Europe, 2010

On Bias in Transition Coverage of Test Sets for Path Delay Faults.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Functional and partially-functional skewed-load tests.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Random Test Generation With Input Cube Avoidance.
IEEE Trans. VLSI Syst., 2009

Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits.
ACM Trans. Design Autom. Electr. Syst., 2009

Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits.
IEEE Trans. Dependable Sec. Comput., 2009

Forward-Looking Reverse Order Fault Simulation for n -Detection Test Sets.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Test compaction methods for transition faults under transparent-scan.
IET Computers & Digital Techniques, 2009

Test vector chains for increasing the fault coverage and numbers of detections.
IET Computers & Digital Techniques, 2009

Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution.
IET Computers & Digital Techniques, 2009

Definition and generation of partially-functional broadside tests.
IET Computers & Digital Techniques, 2009

The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

State persistence: a property for guiding test generation.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Definition and application of approximate necessary assignments.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Partitioned n-detection test generation.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation.
Proceedings of the 14th IEEE European Test Symposium, 2009

Improving the Detectability of Resistive Open Faults in Scan Cells.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

On-chip Generation of the Second Primary Input Vectors of Broadside Tests.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

A scalable method for the generation of small test sets.
Proceedings of the Design, Automation and Test in Europe, 2009

Fault Diagnosis under Transparent-Scan.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

N-distinguishing Tests for Enhanced Defect Diagnosis.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Detectability of internal bridging faults in scan chains.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Dynamic test compaction for a random test generation procedure with input cube avoidance.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion.
IEEE Trans. VLSI Syst., 2008

Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects.
IEEE Trans. VLSI Syst., 2008

On the Saturation of n-Detection Test Generation by Different Definitions With Increased n.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

On Complete Functional Broadside Tests for Transition Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Functional Broadside Tests with Minimum and Maximum Switching Activity.
J. Low Power Electronics, 2008

On the Detectability of Scan Chain Internal Faults - An Industrial Case Study.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Synthesis for Broadside Testability of Transition Faults.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

On Common-Mode Skewed-Load and Broadside Tests.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Detection of Internal Stuck-open Faults in Scan Chains.
Proceedings of the 2008 IEEE International Test Conference, 2008

An Enhanced Logic BIST Architecture for Online Testing.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Safe Fault Collapsing Based on Dominance Relations.
Proceedings of the 13th European Test Symposium, 2008

Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

On Reducing Circuit Malfunctions Caused by Soft Errors.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy.
Proceedings of the Design, Automation and Test in Europe, 2008

On tests to detect via opens in digital CMOS circuits.
Proceedings of the 45th Design Automation Conference, 2008

Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Test vector chains for increased targeted and untargeted fault coverage.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Forming N-detection test sets without test generation.
ACM Trans. Design Autom. Electr. Syst., 2007

z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Invariant States and Redundant Logic in Synchronous Sequential Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Enhancing delay fault coverage through low-power segmented scan.
IET Computers & Digital Techniques, 2007

Effectiveness of scan-based delay fault tests in diagnosis of transition faults.
IET Computers & Digital Techniques, 2007

Worst-case and average-case analysis of n-detection test sets and test generation strategies.
IET Computers & Digital Techniques, 2007

On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits.
Electron. Notes Theor. Comput. Sci., 2007

Scan-Based Tests with Low Switching Activity.
IEEE Design & Test of Computers, 2007

Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Low Shift and Capture Power Scan Tests.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Functional Broadside Tests with Different Levels of Reachability.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

On the saturation of n-detection test sets with increased n.
Proceedings of the 2007 IEEE International Test Conference, 2007

Testing for systematic defects based on DFM guidelines.
Proceedings of the 2007 IEEE International Test Conference, 2007

Diagnostic Test Generation Based on Subsets of Faults.
Proceedings of the 12th European Test Symposium, 2007

Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

A-Diagnosis: A Complement to Z-Diagnosis.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

On test generation by input cube avoidance.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Improved n-Detection Test Sequences Under Transparent Scan.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Using Dummy Bridging Faults to Define Reduced Sets of Target Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Generation of Functional Broadside Tests for Transition Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Scan-BIST based on transition probabilities for circuits with single and multiple scan chains.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan.
IEEE Trans. Computers, 2006

On Finding Don't Cares in Test Sequences for Sequential Circuits.
IEICE Transactions, 2006

Scan Tests with Multiple Fault Activation Cycles for Delay Faults.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Dominance Based Analysis for Large Volume Production Fail Diagnosis.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs.
Proceedings of the 2006 IEEE International Test Conference, 2006

Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences.
Proceedings of the 2006 IEEE International Test Conference, 2006

A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests.
Proceedings of the 2006 IEEE International Test Conference, 2006

A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

A delay fault model for at-speed fault simulation and test generation.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Fault Collapsing for Transition Faults Using Extended Transition Faults.
Proceedings of the 11th European Test Symposium, 2006

A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults.
Proceedings of the 11th European Test Symposium, 2006

Scan-Based Delay Fault Tests for Diagnosis of Transition Faults.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Selecting High-Quality Delay Tests for Manufacturing Test and Debug.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Test Generation for Open Defects in CMOS Circuits.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Test compaction for transition faults under transparent-scan.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A test pattern ordering algorithm for diagnosis with truncated fail data.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Autoscan: a scan design without external scan inputs or outputs.
IEEE Trans. VLSI Syst., 2005

Concurrent Online Testing of Identical Circuits Using Nonidentical Input Vectors.
IEEE Trans. Dependable Sec. Comput., 2005

On fault equivalence, fault dominance, and incompletely specified test sets.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

On masking of redundant faults in synchronous sequential circuits with design-for-testability logic.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

On reducing test application time for scan circuits using limited scan operations and transfer sequences.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Forming N-detection test sets from one-detection test sets without test generation.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Methods for improving transition delay fault coverage using broadside tests.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Fault Diagnosis and Fault Model Aliasing.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

On Reducing Peak Current and Power during Test.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Dynamic Test Compaction for Bridging Faults.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Battery-aware dynamic voltage scaling in multiprocessor embedded system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Path-oriented transition fault test generation considering operating conditions.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

Using dummy bridging faults to define a reduced set of target faults.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

A unified fault model and test generation procedure for interconnect opens and bridges.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

On Generating Pseudo-Functional Delay Fault Tests for Scan Designs.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Recovery During Concurrent On-Line Testing of Identical Circuits.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Defect Aware Test Patterns.
Proceedings of the 2005 Design, 2005

The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits.
Proceedings of the 2005 Design, 2005

Worst-Case and Average-Case Analysis of n-Detection Test Sets.
Proceedings of the 2005 Design, 2005

N-detection under transparent-scan.
Proceedings of the 42nd Design Automation Conference, 2005

Circuit Independent Weighted Pseudo-Random BIST Pattern Generator.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Fault isolation for nonisolated blocks.
IEEE Trans. VLSI Syst., 2004

Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations.
IEEE Trans. VLSI Syst., 2004

On the characterization and efficient computation of hard-to-detect bridging faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Vector-restoration-based static compaction using random initial omission.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Constrained test generation for embedded synchronous sequential circuits with serial-input access.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests.
IEEE Trans. Computers, 2004

A Measure of Quality for n-Detection Test Sets.
IEEE Trans. Computers, 2004

On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit.
IEEE Trans. Computers, 2004

Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units.
IEEE Trans. Computers, 2004

Don't Care Identification and Statistical Encoding for Test Data Compression.
IEICE Transactions, 2004

Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Scan BIST Targeting Transition Faults Using a Markov Source.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Test Application Time Reduction for Scan Circuits Using Limited Scan Operations.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis.
Proceedings of the 2004 Design, 2004

Level of Similarity: A Metric for Fault Collapsing.
Proceedings of the 2004 Design, 2004

Scan-BIST based on transition probabilities.
Proceedings of the 41th Design Automation Conference, 2004

On the generation of scan-based test sets with reachable states for testing under functional operation conditions.
Proceedings of the 41th Design Automation Conference, 2004

On test generation for transition faults with minimized peak power dissipation.
Proceedings of the 41th Design Automation Conference, 2004

Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

A Postprocessing Procedure of Test Enrichment for Path Delay Faults.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Properties of Maximally Dominating Faults.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
On test data volume reduction for multiple scan chain designs.
ACM Trans. Design Autom. Electr. Syst., 2003

Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Test data compression based on input-output dependence.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Theorems for identifying undetectable faults in partial-scan circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Test enrichment for path delay faults using multiple sets of target faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

PROPTEST: a property-based test generator for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Reverse-order-restoration-based static test compaction for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Fault equivalence identification in combinational circuits using implication and evaluation techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Transient-Fault Recovery for Chip Multiprocessors.
IEEE Micro, 2003

On Selecting Testable Paths in Scan Designs.
J. Electronic Testing, 2003

A Low Power Pseudo-Random BIST Technique.
J. Electronic Testing, 2003

SOC Test Scheduling Using Simulated Annealing.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

A Test Interface for Built-In Test of Non-Isolated Scanned Cores.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Optimizing SOC Test Resources Using Dual Sequences.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

An Improved Markov Source Design for Scan BIST.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Static Test Compaction for Multiple Full-Scan Circuits.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A Method to Find Don't Care Values in Test Sequences for Sequential Circuits.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

On Compacting Test Response Data Containing Unknown Values.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

On the Characterization of Hard-to-Detect Bridging Faults.
Proceedings of the 2003 Design, 2003

Test Data Compression Based on Output Dependence.
Proceedings of the 2003 Design, 2003

A New Approach to Test Generation and Test Compaction for Scan Circuits.
Proceedings of the 2003 Design, 2003

On test data compression and n-detection test sets.
Proceedings of the 40th Design Automation Conference, 2003

A scan BIST generation method using a markov source and partial bit-fixing.
Proceedings of the 40th Design Automation Conference, 2003

Test Data Volume Reduction by Test Data Realignment.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

A DFT Approach for Path Delay Faults in Interconnected Circuits.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
n-pass n-detection fault simulation and its applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

On the use of random limited-scan to improve at-speed randompattern testing of scan circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set.
IEEE Trans. Computers, 2002

Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission.
IEEE Trans. Computers, 2002

Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times.
IEEE Trans. Computers, 2002

Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Pseudo Random Patterns Using Markov Sources for Scan BIST.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Transient-Fault Recovery Using Simultaneous Multithreading.
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Don't-Care Identification on Specific Bits of Test Patterns.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Conflict driven techniques for improving deterministic test pattern generation.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

On undetectable faults in partial scan circuits.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Properties of Output Sequences and their Use in Guiding Property-Based Test Generation for Synchronous Sequential Circuits.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Test Data Compression Using Don't-Care Identification and Statistical Encoding.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Fault Isolation Using Tests for Non-Isolated Blocks.
Proceedings of the 2002 Design, 2002

Finding a Common Fault Response for Diagnosis during Silicon Debug.
Proceedings of the 2002 Design, 2002

On output response compression in the presence of unknown output values.
Proceedings of the 39th Design Automation Conference, 2002

On Generating High Quality Tests for Transition Faults.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Test Data Compression Using Don?t-Care Identification and Statistical Encoding.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units.
IEEE Trans. VLSI Syst., 2001

A built-in self-test method for diagnosis of synchronous sequential circuits.
IEEE Trans. VLSI Syst., 2001

Testing of scan circuits containing nonisolated random-logic legacycores.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Forward-looking fault simulation for improved static compaction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

On diagnosis and diagnostic test generation for pattern-dependenttransition faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Vector replacement to improve static-test compaction forsynchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits.
Journal of Systems Architecture, 2001

On the Use of Fault Dominance in n-Detection Test Generation.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

On Improving Static Test Compaction for Sequential Circuits.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

A method to enhance the fault coverage obtained by output response comparison of identical circuits.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

On static test compaction and test pattern ordering for scan designs.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

ITEM: an iterative improvement test generation procedure for synchronous sequential circuits.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Sequence reordering to improve the levels of compaction achievable by static compaction procedures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing.
Proceedings of the 38th Design Automation Conference, 2001

Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits.
Proceedings of the 38th Design Automation Conference, 2001

An Efficient Method to Identify Untestable Path Delay Faults.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

On Pass/Fail Dictionaries for Scan Circuits .
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
On synchronizable circuits and their synchronizing sequences.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

On n-detection test sets and variable n-detection test sets fortransition faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits.
IEEE Trans. Computers, 2000

On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits.
IEEE Trans. Computers, 2000

On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines.
IEEE Trans. Computers, 2000

Static Test Compaction for Scan-Based Designs to Reduce Test Application Time.
J. Electronic Testing, 2000

SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Test Transformation to Improve Compaction by Statistical Encoding.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Fault diagnosis based on parameters of output responses.
Proceedings of the 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 2000

On validating data hold times for flip-flops in sequential circuits.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Selection of potentially testable path delay faults for test generation.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Simulation Based Test Generation for Scan Designs.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Improving the Proportion of At-Speed Tests in Scan BIST.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Test-Point Insertion to Enhance Test Compaction for Scan Designs.
Proceedings of the 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 2000

Functional Test Generation for Full Scan Circuits.
Proceedings of the 2000 Design, 2000

Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits.
Proceedings of the 2000 Design, 2000

On diagnosis of pattern-dependent delay faults.
Proceedings of the 37th Conference on Design Automation, 2000

Reducing test application time for full scan circuits by the addition of transfer sequences.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

On the feasibility of fault simulation using partial circuit descriptions.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Enhanced untestable path analysis using edge graphs.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Static test compaction for synchronous sequential circuits based on vector restoration.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

A comment on "Improving a nonenumerative method to estimate path delay fault coverage".
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits.
IEEE Trans. Computers, 1999

Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A Flexible Path Selection Procedure for Path Delay Fault Testing.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Implication and Evaluation Techniques for Proving Fault Equivalence.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

The effects of test compaction on fault diagnosis.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

On achieving complete coverage of delay faults in full scan circuits using locally available lines.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits.
Proceedings of the IEEE International Conference On Computer Design, 1999

An approach for improving the levels of compaction achieved by vector omission.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Techniques for improving the efficiency of sequential circuit test generation.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

PASTA: Partial Scan to Enhance Test Compaction.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Full Scan Fault Coverage With Partial Scan.
Proceedings of the 1999 Design, 1999

Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences.
Proceedings of the 36th Conference on Design Automation, 1999

Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction.
Proceedings of the 36th Conference on Design Automation, 1999

Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

Vector-Based Functional Fault Models for Delay Faults.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998
On methods to match a test pattern generator to a circuit-under-test.
IEEE Trans. VLSI Syst., 1998

Functional test generation for delay faults in combinational circuits.
ACM Trans. Design Autom. Electr. Syst., 1998

Test sequences to achieve high defect coverage for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Design-for-testability for path delay faults in large combinational circuits using test points.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Techniques for minimizing power dissipation in scan and combinational circuits during test application.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning.
IEEE Trans. Computers, 1998

Delay fault models for VLSI circuits1.
Integr., 1998

Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

On Synchronizing Sequences and Test Sequence Partitioning.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

On Removing Redundant Faults in Synchronous Sequential Circuits.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

On Test Compaction Objectives for Combinational and Sequential Circuits.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

MIX: A Test Generation System for Synchronous Sequential Circuits.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

A diagnostic test generation procedure for synchronous sequential circuits based on test elimination.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Improved built-in test pattern generators based on comparison units for synchronous sequential circuits.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

On finding undetectable and redundant faults in synchronous sequential circuits.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

A Generalized Test Generation Procedure for Path Delay Faults.
Proceedings of the Digest of Papers: FTCS-28, 1998

Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines.
Proceedings of the 1998 Design, 1998

A Synthesis Procedure for Flexible Logic Functions.
Proceedings of the 1998 Design, 1998

Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration.
Proceedings of the 1998 Design, 1998

Test Generation for Synchronous Sequential Circuits to Reduce Storage Requirements.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits .
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Compact test sets for high defect coverage.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

On error correction in macro-based circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

LOCSTEP: a logic-simulation-based test generation procedure.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Test Generation for Multiple State-Table Faults in Finite-State Machines.
IEEE Trans. Computers, 1997

On Dictionary-Based Fault Location in Digital Logic Circuits.
IEEE Trans. Computers, 1997

On n-detection test sequences for synchronous sequential circuits343.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

On Full Reset as a Design-For-Testability Technique.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

On the Detection of Reset Faults in Synchronous Sequential Circuits.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Built-in test generation for synchronous sequential circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

On Generating Test Sets that Remain Valid in the Presence of Undetected Faults.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

ACTIV-LOCSTEP: A Test Generation Procedure Based on Logic Simulation and Fault Activation.
Proceedings of the Digest of Papers: FTCS-27, 1997

On the use of reset to increase the testability of interconnected finite-state machines.
Proceedings of the European Design and Test Conference, 1997

On improving genetic optimization based test generation.
Proceedings of the European Design and Test Conference, 1997

Fault Simulation under the Multiple Observation Time Approach using Backward Implications.
Proceedings of the 34st Conference on Design Automation, 1997

TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

On the Compaction of Test Sets Produced by Genetic Optimization.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits.
IEEE Trans. Computers, 1996

On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences.
IEEE Trans. Computers, 1996

On minimizing the number of test points needed to achieve complete robust path delay fault testability.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

On the effects of test compaction on defect coverage.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Synchronization of large sequential circuits by partial reset.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

On Potential Fault Detection in Sequential Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Fault Location Based on Circuit Partitioning.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

On Double Transition Faults as a Delay Fault Model.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques.
Proceedings of the Digest of Papers: FTCS-26, 1996

On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem.
Proceedings of the 1996 European Design and Test Conference, 1996

On Static Compaction of Test Sequences for Synchronous Sequential Circuits.
Proceedings of the 33st Conference on Design Automation, 1996

Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approach.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
NEST: a nonenumerative test generation method for path delay faults in combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

On correction of multiple design errors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing.
IEEE Trans. Computers, 1995

On Fault Simulation for Synchronous Sequential Circuits.
IEEE Trans. Computers, 1995

Aliasing Computation Using Fault Simulation with Fault Dropping.
IEEE Trans. Computers, 1995

An optimal algorithm for cycle breaking in directed graphs.
J. Electronic Testing, 1995

Compact test generation for bridging faults under I/sub DDQ/ testing.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

On generating compact test sequences for synchronous sequential circuits.
Proceedings of the Proceedings EURO-DAC'95, 1995

On Synthesis-for-Testability of Combinational Logic Circuits.
Proceedings of the 32st Conference on Design Automation, 1995

Static compaction for two-pattern test sets.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994
On determining symmetries in inputs of logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

On achieving complete fault coverage for sequential machines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation.
IEEE Trans. Computers, 1994

Application of Homing Sequences to Synchronous Sequential Circuit Testing.
IEEE Trans. Computers, 1994

On identifying undetectable and redundant faults in synchronous sequential circuits.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

On compacting test sets by addition and removal of test vectors.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

On testing delay faults in macro-based combinational circuits.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Test Pattern Generation for Path Delay Faults in Synchronous Sequential Circuits Using Multiple Fast Clocks and Multiple Observations Times.
Proceedings of the Digest of Papers: FTCS/24, 1994

On Codeword Testing of Two-Rail and Parity TSC Checkers.
Proceedings of the Digest of Papers: FTCS/24, 1994

On Improving Fault Diagnosis for Synchronous Sequential Circuits.
Proceedings of the 31st Conference on Design Automation, 1994

Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points.
Proceedings of the 31st Conference on Design Automation, 1994

1993
COMPACTEST: a method to generate compact test sets for combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

STOIC: state assignment based on output/input functions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Testing of Fault-Tolerant Hardware Through Partial Control of Inputs.
IEEE Trans. Computers, 1993

Classification of Faults in Synchronous Sequential Circuits.
IEEE Trans. Computers, 1993

On the Generation of Weights for Weighted Pseudo Random Testing.
Proceedings of the Sixth International Conference on VLSI Design, 1993

A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Fault dictionary compression and equivalence class computation for sequential circuits.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

On diagnosis and correction of design errors.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Test generation for path delay faults based on learning.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Theory and Practice of Sequential Machine Testing and Testability.
Proceedings of the Digest of Papers: FTCS-23, 1993

Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity.
Proceedings of the Digest of Papers: FTCS-23, 1993

EXOP (Extended Operation): A New Logical Fault Model for Digital Circuits.
Proceedings of the Digest of Papers: FTCS-23, 1993

A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis.
Proceedings of the European Design Automation Conference 1993, 1993

GAFPGA: Genetic algorithm for FPGA technology mapping.
Proceedings of the European Design Automation Conference 1993, 1993

NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

The Multiple Observation Time Test Strategy.
IEEE Trans. Computers, 1992

Generalization of independent faults for transition faults.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set.
Proceedings of the Fifth International Conference on VLSI Design, 1992

Effect of Communication in a Parallel Genetic Algorithm.
Proceedings of the 1992 International Conference on Parallel Processing, 1992

COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

An efficient non-enumerative method to estimate path delay fault coverage.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

On the generation of small dictionaries for fault location.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

A Divide-And-Conquer Approach to Test Generation for Large Synchronous Sequential Circuits.
Proceedings of the Digest of Papers: FTCS-22, 1992

Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability.
Proceedings of the Digest of Papers: FTCS-22, 1992

SPADES: a simulator for path delay faults in sequential circuits.
Proceedings of the conference on European design automation, 1992

At-Speed Delay Testing of Synchronous Sequential Circuits.
Proceedings of the 29th Design Automation Conference, 1992

State Assignment Using Input/Output Functions.
Proceedings of the 29th Design Automation Conference, 1992

1991
Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing Module Insertion.
IEEE Trans. Computers, 1991

The minimum test set problem for circuits with nonreconvergent fanout.
J. Electronic Testing, 1991

COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Achieving Complete Delay Fault Testability by Extra Inputs.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Testing of Fault-Tolerant Hardware.
Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991

Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Test Generation for Synchronous Sequential Circuits Based on Fault Extraction.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times.
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model.
Proceedings of the 28th Design Automation Conference, 1991


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