Siwei Xiang

According to our database, Siwei Xiang authored at least 9 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture.

Jianfei Wang, Chen Yang, Fahong Zhang, Jia Hou, Yishuo Meng, Siwei Xiang, Yang Su

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units.

Chen Yang, Yaoyao Yang, Yishuo Meng, Kaibo Huo, Siwei Xiang, Jianfei Wang, Li Geng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks.

Chen Yang, Yishuo Meng, Jiawei Xi, Siwei Xiang, Jianfei Wang, Kuizhi Mei

IEEE Trans. Very Large Scale Integr. Syst., January, 2024

A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm.

Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Siwei Xiang, Yang Su

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

2023

A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access.

Chen Yang, Junfeng Wu, Siwei Xiang, Liyan Liang, Li Geng

IEEE Trans. Very Large Scale Integr. Syst., October, 2023

An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling Workflow.

Yishuo Meng, Chen Yang, Siwei Xiang, Jianfei Wang, Kuizhi Mei, Li Geng

IEEE Trans. Very Large Scale Integr. Syst., October, 2023

POSS-CNN: An Automatically Generated Convolutional Neural Network with Precision and Operation Separable Structure Aiming at Target Recognition and Detection.

Jia Hou, Jingyu Zhang, Qi Chen, Siwei Xiang, Yishuo Meng, Jianfei Wang, Cimang Lu, Chen Yang

Inf., 2023

An Efficient Hardware Implementation of Dilated Convolution Using a Novel Channel-Equivalent Decomposition Method.

Yuheng Xia, Yishuo Meng, Siwei Xiang, Jianfei Wang, Chen Yang

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

2021

A High Performance and Full Utilization Hardware Implementation of Floating Point Arithmetic Units.

Chen Yang, Siwei Xiang, Jiaxing Wang, Liyan Liang

Proceedings of the 28th IEEE International Conference on Electronics, 2021