Chen Yang
Orcid: 0000-0002-8221-7670Affiliations:
- Xi'an Jiaotong University, School of Microelectronics, China
According to our database1,
Chen Yang
authored at least 33 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024
WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024
A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
An Efficient and Scalable FHE-Based PDQ Scheme: Utilizing FFT to Design a Low Multiplication Depth Large-Integer Comparison Algorithm.
IEEE Trans. Inf. Forensics Secur., 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling Workflow.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023
J. Ambient Intell. Humaniz. Comput., July, 2023
POSS-CNN: An Automatically Generated Convolutional Neural Network with Precision and Operation Separable Structure Aiming at Target Recognition and Detection.
Inf., 2023
An Efficient Hardware Implementation of Dilated Convolution Using a Novel Channel-Equivalent Decomposition Method.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
2022
A Sparse CNN Accelerator for Eliminating Redundant Computations in Intra- and Inter-Convolutional/Pooling Layers.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication.
IEEE Trans. Very Large Scale Integr. Syst., 2022
ReMCA: A Reconfigurable Multi-Core Architecture for Full RNS Variant of BFV Homomorphic Evaluation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
RNA: A Flexible and Efficient Accelerator Based on Dynamically Reconfigurable Computing for Multiple Convolutional Neural Networks.
J. Circuits Syst. Comput., 2022
SDF-SLAM: A Deep Learning Based Highly Accurate SLAM Using Monocular Camera Aiming at Indoor Map Reconstruction With Semantic and Depth Fusion.
IEEE Access, 2022
Proceedings of the IECON 2022, 2022
2021
UL-CNN: An Ultra-Lightweight Convolutional Neural Network Aiming at Flash-Based Computing-In-Memory Architecture for Pedestrian Recognition.
J. Circuits Syst. Comput., 2021
A Lightweight Full Homomorphic Encryption Scheme on Fully-connected Layer for CNN Hardware Accelerator achieving Security Inference.
Proceedings of the 28th IEEE International Conference on Electronics, 2021
2020
A Stride-Based Convolution Decomposition Method to Stretch CNN Acceleration Algorithms for Efficient and Flexible Hardware Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Access, 2020
CRP: Context-directed Replacement Policy to Improve Cache Performance for Coarse-Grained Reconfigurable Arrays.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
WRA: A 2.2-to-6.3 TOPS Highly Unified Dynamically Reconfigurable Accelerator Using a Novel Winograd Decomposition Algorithm for Convolutional Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A Fully Quantitative Scheme With Fine-grained Tuning Method For Lightweight CNN Acceleration.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
CCP: Configuration Context based Prefetching to Improve Coarse-Grained Reconfigurable Array Performance.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
2017
CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays.
IEEE Trans. Parallel Distributed Syst., 2017
2016
Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array.
J. Circuits Syst. Comput., 2015
Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
2014
Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014