Sixiao Huang
Orcid: 0000-0002-2252-0678
According to our database1,
Sixiao Huang
authored at least 7 papers
between 2022 and 2025.
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Bibliography
2025
A Tensor-Train Decomposition based Compression of LLMs on Group Vector Systolic Accelerator.
CoRR, January, 2025
An MLA-LLM Hardware Acceleration with Tensor-Train Decomposition on Group Vector Systolic Accelerator.
Proceedings of the 36th IEEE International Conference on Application-specific Systems, 2025
2024
LAMPS: A Layer-wised Mixed-Precision-and-Sparsity Accelerator for NAS-Optimized CNNs on FPGA.
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024
2023
An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023
2022
A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022