Mingqiang Huang
Orcid: 0000-0002-7794-3985
According to our database1,
Mingqiang Huang
authored at least 17 papers
between 2017 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023
RRAM-Based Precision-Scaleable Computing-In-Memory Scheme and Its Error Correction Approach.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
Group Vectored Absolute-Value-Subtraction Cell Array for the Efficient Acceleration of AdderNet.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022
A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
A General-Purpose and Configurable Planar Data Processor for Energy-Efficient Pooling Computation.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
AdderNet and its Minimalist Hardware Design for Energy-Efficient Artificial Intelligence.
CoRR, 2021
Hardware-Friendly Stochastic and Adaptive Learning in Memristor Convolutional Neural Networks.
Adv. Intell. Syst., 2021
Proceedings of the 38th International Conference on Machine Learning, 2021
2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017