Wei Mao
Orcid: 0000-0003-2527-6778Affiliations:
- HiSilicon Technologies Co., Ltd., Shenzhen, China
- National University of Singapore (NUS), Singapore (PhD 2017)
- Southeast University, Department of electronic science and technology, Nanjing, China
According to our database1,
Wei Mao
authored at least 30 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
2023
APCCAS 2022 Guest Editorial Special Issue Based on the 18th Asia Pacific Conference on Circuits and Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023
A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
RISC-V based Fully-Parallel SRAM Computing-in-Memory Accelerator with High Hardware Utilization and Data Reuse Rate.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
A Fall Detection Network by 2D/3D Spatio-temporal Joint Models with Tensor Compression on Edge.
ACM Trans. Embed. Comput. Syst., November, 2022
A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2022
An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection.
IEEE Des. Test, 2022
BaseFormer: Transformer based Base-Caller for Fast and Accurate Next Generation Sequencing.
Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022
A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
An Energy-Efficient Bit-Split-and-Combination Systolic Accelerator for NAS-Based Multi-Precision Convolution Neural Networks.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Hierarchical DNN with Heterogeneous Computing Enabled High-Performance DNA Sequencing.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
An Energy-Efficient Mixed-Bit ReRAM-based Computing-in-Memory CNN Accelerator with Fully Parallel Readout.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A Low-Power Approximate Multiplier with Sign-Focus Compressor and Error Compensation.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
A Reconfigurable Multiple-Precision Floating-Point Dot Product Unit for High-Performance Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
A Video-based Fall Detection Network by Spatio-temporal Joint-point Model on Edge Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Multiple-Precision Floating-Point Dot Product Unit for Efficient Convolution Computation.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 74-μW 11-Mb/s Wireless Vital Signs Monitoring SoC for Three-Lead ECG, Respiration Rate, and Body Temperature.
IEEE Trans. Biomed. Circuits Syst., 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A 93μW 11Mbps wireless vital signs monitoring SoC with 3-lead ECG, bio-impedance, and body temperature.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
Dynamic mapping method for static and dynamic performance improvement on current-steering digital-to-analog converter.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2014
An ultra-low voltage comparator with improved comparison time and reduced offset voltage.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014