Snaider Carrillo

According to our database1, Snaider Carrillo authored at least 12 papers between 2009 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2015
Hierarchical Networks-on-Chip Architecture for Neuromorphic Hardware.
Proceedings of the Evolvable Hardware - From Practice to Application, 2015

2013
Scalable hierarchical networks-on-chip architecture for brain-inspired computing.
PhD thesis, 2013

Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations.
IEEE Trans. Parallel Distrib. Syst., 2013

Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network.
Neural Processing Letters, 2013

2012
Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers.
Neural Networks, 2012

Investigating Power Reduction for NoC-Based Spiking Neural Network Platforms using Channel Encoding.
IJARAS, 2012

Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

2011
Hardware spiking neural network prototyping and application.
Genetic Programming and Evolvable Machines, 2011

Addressing the Hardware Resource Requirements of Network-on-chip based Neural Architectures.
Proceedings of the NCTA 2011, 2011

Adaptive Routing Strategies for Large Scale Spiking Neural Network Hardware Implementations.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2011, 2011

2010
An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2010

2009
A control-structure splitting optimization for GPGPU.
Proceedings of the 6th Conference on Computing Frontiers, 2009


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