Sandeep Pande

According to our database1, Sandeep Pande authored at least 13 papers between 2010 and 2019.

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Bibliography

2019
ECG-based Heartbeat Classification in Neuromorphic Hardware.
Proceedings of the International Joint Conference on Neural Networks, 2019

Applications of Computation-In-Memory Architectures based on Memristive Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Power-Accuracy Trade-Offs for Heartbeat Classification on Neural Networks Hardware.
J. Low Power Electronics, 2018

2017
Rapid application prototyping for hardware modular spiking neural network architectures.
Neural Computing and Applications, 2017

2013
Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations.
IEEE Trans. Parallel Distrib. Syst., 2013

Fixed latency on-chip interconnect for hardware spiking neural network architectures.
Parallel Computing, 2013

Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network.
Neural Processing Letters, 2013

2012
Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers.
Neural Networks, 2012

Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

2011
Hardware spiking neural network prototyping and application.
Genetic Programming and Evolvable Machines, 2011

Addressing the Hardware Resource Requirements of Network-on-chip based Neural Architectures.
Proceedings of the NCTA 2011, 2011

Adaptive Routing Strategies for Large Scale Spiking Neural Network Hardware Implementations.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2011, 2011

2010
An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2010


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