Fearghal Morgan

According to our database1, Fearghal Morgan authored at least 46 papers between 2001 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Web-Based Interfaces for Virtual C. elegans Neuron Model Definition, Network Configuration, Behavioral Experiment Definition and Experiment Results Visualization.
Front. Neuroinform., 2018

Vicilogic 2.0: Online Learning and Prototyping of Digital Systems Using PYNQ-Z1/-Z2 SoC.
Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018

viciLogic2.0 Online Learning and Prototyping Using PYNQ.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
Rapid application prototyping for hardware modular spiking neural network architectures.
Neural Computing and Applications, 2017

Evaluation and Comparison of Low FPGA Footprint, Embedded Soft-Core Processors.
Proceedings of the International Conference on Recent Achievements in Mechatronics, 2017

2016
Astrocyte to spiking neuron communication using Networks-on-Chip ring topology.
Proceedings of the 2016 IEEE Symposium Series on Computational Intelligence, 2016

Embedded Real-time Implementation of a Computational Efficient Optical Flow Extraction Method for Intelligent Robot Control Applications.
Proceedings of the 24th Irish Conference on Artificial Intelligence and Cognitive Science, 2016

2015
Web-enabled Neuron Model Hardware Implementation and Testing.
Proceedings of the 3rd International Congress on Neurotechnology, 2015

2014
Neuron Models in FPGA Hardware - A Route from High Level Descriptions to Hardware Implementations.
Proceedings of the 2nd International Congress on Neurotechnology, 2014

Exploring Neural Principles with Si elegans, a Neuromimetic Representation of the Nematode Caenorhabditis elegans.
Proceedings of the 2nd International Congress on Neurotechnology, 2014

The Si elegans Project - The Challenges and Prospects of Emulating Caenorhabditis elegans.
Proceedings of the Biomimetic and Biohybrid Systems - Third International Conference, 2014

2013
Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations.
IEEE Trans. Parallel Distrib. Syst., 2013

Fixed latency on-chip interconnect for hardware spiking neural network architectures.
Parallel Computing, 2013

Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network.
Neural Processing Letters, 2013

The Influence of Cell Type on Artificial Development.
Proceedings of the Twelfth European Conference on the Synthesis and Simulation of Living Systems: Advances in Artificial Life, 2013

2012
Remote FPGA Lab for Enhancing Learning of Digital Systems.
TRETS, 2012

Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers.
Neural Networks, 2012

Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

2011
Maintaining Healthy Population Diversity Using Adaptive Crossover, Mutation, and Selection.
IEEE Trans. Evolutionary Computation, 2011

Hardware spiking neural network prototyping and application.
Genetic Programming and Evolvable Machines, 2011

Enhancing learning of digital systems using a remote FPGA lab.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Addressing the Hardware Resource Requirements of Network-on-chip based Neural Architectures.
Proceedings of the NCTA 2011, 2011

Adaptive Routing Strategies for Large Scale Spiking Neural Network Hardware Implementations.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2011, 2011

Remote FPGA Lab with Interactive Control and Visualisation Interface.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

ERDB: An Embedded Routing Database for Reconfigurable Systems.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010
Guest Editorial ARC 2009.
TRETS, 2010

Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems.
TRETS, 2010

SeReCon: a secure reconfiguration controller for self-reconfigurable systems.
IJCCBS, 2010

An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2010

2009
A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks.
Int. J. Reconfig. Comp., 2009

IP protection in Partially Reconfigurable FPGAs.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Evolving plastic responses in artificial cell models.
Proceedings of the IEEE Congress on Evolutionary Computation, 2009

FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
SeReCon: A Secure Dynamic Partial Reconfiguration Controller.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Investigating the Suitability of FPAAs for Evolved Hardware Spiking Neural Networks.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2008

Reconfigurable analogue hardware evolution of adaptive spiking neural network controllers.
Proceedings of the Genetic and Evolutionary Computation Conference, 2008

Maintaining diversity through adaptive selection, crossover and mutation.
Proceedings of the Genetic and Evolutionary Computation Conference, 2008

Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks.
Proceedings of the FPL 2008, 2008

SeReCon: A Trusted Environment for SoPC Design.
Proceedings of the Third International Conference on Dependability of Computer Systems, 2008

2007
Run-Time Management of Reconfigurable Hardware Tasks Using Embedded Linux.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
Transparent Management of Reconfigurable Hardware in Embedded Operating Systems.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital Devices.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2005
Platform for intrinsic evolution of analogue neural networks.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005

Applied VHDL training methodology, EDA framework and hardware implementation platform.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005

2001
Xilinx FPGA implementation of an image classifier for object detection applications.
Proceedings of the 2001 International Conference on Image Processing, 2001


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