Sonal Yadav

Orcid: 0000-0002-0608-567X

According to our database1, Sonal Yadav authored at least 22 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A Review of Feature Extraction and Classification Techniques in Speech Recognition.
SN Comput. Sci., November, 2023

Adaptive distribution of control messages for improving bandwidth utilization in multiple NoC.
J. Supercomput., October, 2023

Stable sharing.
Games Econ. Behav., September, 2023

Retinal Detachment Dataset.
Dataset, February, 2023

2022
Power efficient network selector placement in control plane of multiple networks-on-chip.
J. Supercomput., 2022

Real-time interception performance evaluation of certain proportional navigation based guidance laws in aerial ground engagement.
Intell. Serv. Robotics, 2022

i-MAX: Just-In-Time Wakeup of Maximally Gated Router for Power Efficient Multiple NoC.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2021
AdCOFE: Advanced Contextual Feature Extraction in conversations for emotion classification.
PeerJ Comput. Sci., 2021

Local global equivalence for unanimous social choice functions.
Games Econ. Behav., 2021

2020
Multiple-NoC Exploration and Customization for Energy Efficient Traffic Distribution.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

2019
Matching with partners and projects.
J. Econ. Theory, 2019

Lightweight Message Encoding of Power-Gating Controller for On-Time Wakeup of Gated Router in Network-on-Chip.
Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2019

Improving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
A Power Efficient Crossbar Arbitration in Multi-NoC for Multicast and Broadcast Traffic.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

2017
A Power, Thermal and Reliability-Aware Network-on-Chip.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2016
Selecting winners with partially honest jurors.
Math. Soc. Sci., 2016

A Power Efficient Dual Link Mesh NoC Architecture to Support Nonuniform Traffic Arbitration at Routing Logic.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015
A Hurwicz type result in a model with public good production.
Soc. Choice Welf., 2015

C<sup>2</sup>-DLM: Cache coherence aware dual link mesh for on-chip interconnect.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014
Dynamic fault injection model for on-chip 2D mesh network.
Proceedings of the 7th ACM India Computing Conference, 2014

2013
Energy Scavenging Based HybridGSM Model for Mobile Towers.
Proceedings of the Recent Advances in Intelligent Informatics, 2013

Ns-3 emulation on ORBIT testbed.
Proceedings of the International Conference on Advances in Computing, 2013


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