Ashish Sharma

Affiliations:
  • Manipal University Jaipur, Department of Computer Science and Engineering, Jaipur, India
  • Indian Institute of Information Technology (IIIT) Kota, Department of Computer Science and Engineering, Kota, India
  • Malaviya National Institute of Technology, Jaipur, India (PhD 2019)


According to our database1, Ashish Sharma authored at least 15 papers between 2014 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2025
iSeizdiag: toward the framework development of epileptic seizure detection for healthcare.
Frontiers Comput. Neurosci., 2025

SRCPAR - Spike Response-Based Congestion Prediction for Adaptive Routing for 2D NoCs.
IEEE Access, 2025

2024
Optimized Mirror Generative Adversarial Network with BERT Neural Architecture for Text Caption to Image Conversion.
SN Comput. Sci., April, 2024

The Internet of Trust: Securing and Transparent Supply Chains with Blockchain and IoT.
Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2024

2023
An improved reconfiguration algorithm for handling 1-point NoC failures.
Microprocess. Microsystems, 2023

2022
Pre-Silicon NBTI Delay-Aware Modeling of Network-on-Chip Router Microarchitecture.
Microprocess. Microsystems, June, 2022

Heart rate and blood pressure measurement based on photoplethysmogram signal using fast Fourier transform.
Comput. Electr. Eng., 2022

2018
3D LBDR: Logic-Based Distributed Routing for 3D NoC.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

2017
A Power, Thermal and Reliability-Aware Network-on-Chip.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2016
<i>σ</i> <sup> <i>n</i> </sup>LBDR: generic congestion handling routing implementation for two-dimensional mesh network-on-chip.
IET Comput. Digit. Tech., 2016

Reducing FIFO buffer power using architectural alternatives at RTL.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015
A framework for thermal aware reliability estimation in 2D NoC.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Network-on-chip: Current issues and challenges.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Characterizing impacts of multi-Vt routers on power and reliability of Network-on-Chip.
Proceedings of the Eighth International Conference on Contemporary Computing, 2015

2014
Improved Route Selection Approaches using Q-learning framework for 2D NoCs.
Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES'2015) held on June 13, 2014


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