Hemangee K. Kapoor
Orcid: 0000-0002-9376-7686Affiliations:
- Indian Institute of Technology Guwahati, India
According to our database1,
Hemangee K. Kapoor
authored at least 112 papers
between 2004 and 2024.
Collaborative distances:
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Online presence:
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on iitg.ac.in
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on acm.org
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on orcid.org
On csauthors.net:
Bibliography
2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
2023
Adaptive distribution of control messages for improving bandwidth utilization in multiple NoC.
J. Supercomput., October, 2023
ACM Trans. Embed. Comput. Syst., March, 2023
ALAMNI: Adaptive LookAside Memory Based Near-Memory Inference Engine for Eliminating Multiplications in Real-Time.
IEEE Trans. Computers, March, 2023
CADEN: Compression-Assisted Adaptive Encoding to Improve Lifetime of Encrypted Nonvolatile Main Memories.
IEEE Embed. Syst. Lett., March, 2023
CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM Caches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in Neural Network Inference.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
ZOCHEN: Compression Using Zero Chain Elimination and Encoding to Improve Endurance of Non-Volatile Memories.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the 23rd IEEE/ACM International Symposium on Cluster, 2023
2022
Pop-Crypt: Identification and Management of Popular Words for Enhancing Lifetime of EnCrypted Nonvolatile Main Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2022
CORIDOR: Using COherence and TempoRal LocalIty to Mitigate Read Disurbance ErrOR in STT-RAM Caches.
ACM Trans. Embed. Comput. Syst., 2022
SWEL-COFAE : Wear Leveling and Adaptive Encoding Assisted Compression of Frequent Words in Non-Volatile Main Memories.
IEEE Trans. Computers, 2022
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
i-MAX: Just-In-Time Wakeup of Maximally Gated Router for Power Efficient Multiple NoC.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
Exploiting successive identical words and differences with dynamic bases for effective compression in Non-Volatile Memories.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
CoSeP: Compression and Content-based Selection Procedure to Improve Lifetime of Encrypted Non-Volatile Main Memories.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
SRS-Mig: Selection and Run-time Scheduling of page Migration for improved response time in hybrid PCM-DRAM memories.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
DEI activities at the ACM and How to make CS education more inclusive: Keynote Abstract.
Proceedings of the COMPUTE 2022, Jaipur, India, November 9-11, 2022, 2022
CluSpa: Computation Reduction in CNN Inference by exploiting Clustering and Sparsity.
Proceedings of the Second International Conference on AI-ML Systems, 2022
2021
ACM Trans. Embed. Comput. Syst., 2021
Investigating Frequency Scaling, Nonvolatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark Silicon.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
J. Syst. Archit., 2021
CLU: A Near-Memory Accelerator Exploiting the Parallelism in Convolutional Neural Networks.
ACM J. Emerg. Technol. Comput. Syst., 2021
Proceedings of the 27th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2021
SeNonDiv: Securing Non-Volatile Memory using Hybrid Memory and Critical Data Diversion.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the 12th International Conference on Computing Communication and Networking Technologies, 2021
2020
Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System.
ACM Trans. Design Autom. Electr. Syst., 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
LiNoVo: Longevity Enhancement of Non-Volatile Last Level Caches in Chip Multiprocessors.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
WELCOMF: wear leveling assisted compression using frequent words in non-volatile main memories.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Write Variation Aware Buffer Assignment for Improved Lifetime of Non-Volatile Buffers in On-Chip Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2019
ACM Trans. Design Autom. Electr. Syst., 2019
IEEE Trans. Computers, 2019
Dynamic reconfiguration of embedded-DRAM caches employing zero data detection based refresh optimisation.
J. Syst. Archit., 2019
J. Parallel Distributed Comput., 2019
Write-variation aware alternatives to replace SRAM buffers with non-volatile buffers in on-chip interconnects.
IET Comput. Digit. Tech., 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Write Variation Aware Cache Partitioning for Improved Lifetime in Non-volatile Caches.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 2019
Lightweight Message Encoding of Power-Gating Controller for On-Time Wakeup of Gated Router in Network-on-Chip.
Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Enhancing the Lifetime of Non-Volatile Caches by Exploiting Module-Wise Write Restriction.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Improving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Sustain. Comput., 2018
Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
A Power Efficient Crossbar Arbitration in Multi-NoC for Multicast and Broadcast Traffic.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018
Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018
Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018
Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
2017
IEEE Trans. Parallel Distributed Syst., 2017
Performance linked dynamic cache tuning: A static energy reduction approach in tiled CMPs.
Microprocess. Microsystems, 2017
Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques.
Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017
Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
2016
A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture.
ACM Trans. Design Autom. Electr. Syst., 2016
Comput. Informatics, 2016
Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016
Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016
2015
VLSI Design, 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Static energy reduction by performance linked cache capacity management in tiled CMPs.
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015
2014
Microprocess. Microsystems, 2014
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Proceedings of the 2014 International Conference on Information Technology, 2014
Proceedings of the 2014 International Conference on Information Technology, 2014
2013
Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors.
J. Supercomput., 2013
Formal Approach for DVS-Based Power Management for Multiple Server System in Presence of Server Failure and Repair.
IEEE Trans. Ind. Informatics, 2013
Circuits Syst. Signal Process., 2013
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Proceedings of the IEEE 11th International Conference on Dependable, 2013
2011
Proceedings of the International Symposium on Electronic System Design, 2011
2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Proceedings of the 8th IEEE International Conference on Control and Automation, 2010
2009
2007
Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007
2006
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments.
Fundam. Informaticae, 2006
Proceedings of the Fourth IEEE International Conference on Software Engineering and Formal Methods (SEFM 2006), 2006
2005
Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation.
Proceedings of the Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 2005
2004
Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench.
Inf. Process. Lett., 2004
Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis.
Proceedings of the 41th Design Automation Conference, 2004